Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Quartus 20.1.0 Synthesis of System Verilog Interfaces


I have basic interfaces with modports as below:


interface if_memory (

logic valid;
logic strobe;
logic wren;
logic [31:0] address;

modport client (
input valid,
output strobe, wren, address

modport host (
output valid,
input strobe, wren, address


when I synthesize these interfaces connected between modules, I get the following warning:

Warning (12158): Entity "if_memory" contains only dangling pins

 I connect these interfaces using the following basic assignments

if_memory if_memory();
assign some_strobe = if_memory.strobe;
assign some_wren = if_memory.wren;
assign some_address = if_memory.address;


With the some_block using the interface:


some_block some_block (


With some_block as 

module some_block (

// memory interface
if_memory if_memory,

I've also tried if_memory.client as the port declaration, and passing in if_memory.

What is going on here? The only interfaces that do not have this dangling issue are clocked interfaces. 


Also, where are the system verilog capabilities for 20.1.0 that were last present in documents for 17.0?


Note that what I have above matches Intel examples for interfaces - is there some setting that I am missing?


When i change the interfaces to ports - the designs work on the chip as expected.

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4 Replies

Hi @bitstreamer 


I am not familiar with modports but you may checkout the IEEE Standard for SystemVerilog (Section 25.5 Modports) document for code example.

Or you may checkout the webpage below on how to code it.


May I know which documents that you refer to previously, that stated the system verilog capabilities for Quartus17.0? 

You may checkout the webpage below for further information on SystemVerilog Synthesis Support in Intel Quartus Prime Software.


Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos. 


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I swear Richard, you are the only person that works at Intel! You've answered all of my questions over years.

The link is here, ends at 17.0:

It appears that Quartus does not synthesize interface logic consistently.  The problem isn't with the usage of system verilog, since the design simulates fine.

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Hi @bitstreamer 


You mentioned that the Quartus does not synthesize interface logic consistently, may I further understand the issue behind? 

I found that Quartus has interface template that you can use, perhaps you can try to synthesis using the Interface template provided, to check if the issue still persists? 


1. In the new .sv file created, Right-click and scroll to Insert template

2. A window will pop up. Click SystemVerilog > Design Units > Interfaces


Interface Declaration Template: 

interface <interface_name>(<port_list>);

	// Variable Declaration(s)
	// Modport Declaration(s)
	// Function/Task Declaration(s)
	// Always Construct(s)
	// Generate(s)
	// An interface cannot instantiate a module but it may
	// instantiate an interface



Modport Declaration Template: 

// A modport limits the access to the objects in an interface.  Each port
// must correspond to an object in the enclosing interface.  
modport <modport_name>(<port_list>);

// Examples
modport slave(input clk, input sel, output byte data);
modport master(input clk, output sel, input byte data);


Fyi, we have a team of people working on Intel Forum, and I believe you will most likely find me or my colleagues, on questions related to Quartus tool. Perhaps you may help to share us your feedback regarding to the forum support for the past few years? 


Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos. 


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Hi Richard - 


I'm unable to give kudos again for some reason - i get the white circle with a bar.

That is a great reference for interfaces within quartus - but it confirms the two things I am indicating - quartus doesn't handle logic within the interface, and the documentation stopped indicating levels of support for system verilog in version 17.0.


If you look at the templates, the ones that contain logic are actually *outside* of the interface. I personally cannot see a reason for this from a synthesis point of view. Quartus models (from the netlist viewer) Interface logic as a separate block, that acts like a 'punchboard' of wire connections. Each interface port when instantiated to a cone of logic, become a buffer within an RTL build.


I have to accept whatever is decided in Santa Clara. Given that, when logic is inserted, and accepted by most other tools, when Quartus reads that RTL, it doesn't produce an error or warning, indicating that RTL logic in interfaces is an issue. The only sign I saw was that Quartus would put warnings on wire assignments in interfaces connected to interface logic that the wire assignment had no initialization, from a synthesis and even a copper perspective, doesn't make sense at all.


So if Quartus doesn't support synthesis of logic in templates (which the interfaces you provided seem to confirm) it should error when any interface contains logic.


Yes, I submit feedback regularly. Thank you for your response.


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