Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
16736 Discussions

Quartus 21.1: Error (10170): Verilog HDL syntax error at ... near text: "import"; expecting ";".

AEsqu
Novice
7,333 Views

module ethosu55_sb
import ethosu55_pkg::*;
import ethosu55_mac_pkg::*;
#(
parameter npu_config_t CFG = BUILD_CFG(0,0)
)

Gives this quartus error:
Error (10170): Verilog HDL syntax error at ethosu55_sb.sv(22) near text: "import"; expecting ";".
Check for and fix any syntax errors that appear immediately before or at the specified keyword.
The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error.
Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

 

Synplify has no problem with it.

How to solve this without changing the ARM RTL code?

Kind Regards,

Alex.

 

 

0 Kudos
4 Replies
AEsqu
Novice
7,325 Views

I dowload the related imported package using this in the .qsf:

set_global_assignment -name SYSTEMVERILOG_FILE -lib ethosu55_lib ${data}/ip_arm_lib/ip_hactar_256/ethosu55/logical/ethosu55/verilog/ethosu55_pkg.sv

 

set_global_assignment -name SYSTEMVERILOG_FILE -lib ethosu55_lib ${data}/ip_arm_lib/ip_hactar_256/ethosu55/logical/ethosu55_mac/verilog/ethosu55_mac_pkg.sv

 

And the RTL itself that contains the import (later in the qsf, not before the two previous files):

 

set_global_assignment -name SYSTEMVERILOG_FILE -lib ethosu55_lib ${data}/ip_arm_lib/ip_hactar_256/ethosu55/logical/ethosu55_sb/verilog/ethosu55_sb.sv

 

0 Kudos
AEsqu
Novice
7,325 Views

The header file mention this:

//-----------------------------------------------------------------------------
// SystemVerilog (IEEE Std 1800-2012)
//-----------------------------------------------------------------------------

0 Kudos
YEan
Employee
7,294 Views

Hi Alex,

 

Do you have any update on you problem?

 

Regards,

Ean

0 Kudos
sstrell
Honored Contributor III
7,320 Views

I've never used this, but it looks like the import commands need to be inside your module (after the port list and semicolon), not in the module declaration, or completely outside the module.

https://blogs.sw.siemens.com/verificationhorizons/2020/07/15/what-does-importing-a-systemverilog-package-mean/

https://verilogguide.readthedocs.io/en/latest/verilog/package.html

 

0 Kudos
Reply