Quartus 22.1std Access Violation quartus_map.exe Stratix V

[TomCarpenter]

Hi,

When compiling a project for a Stratix V device using Quartus 22.1std on a Windows 10 machine. The design uses multiple design partitions including two which contain UniPHY memory controllers in case that matters.

The synthesis step crashes with the following access violation error message:

Problem Details
Error:

*** Fatal Error: Access Violation at 00007FFBAB5E4C6A
Module: quartus_map.exe
Stack Trace:
     0x4c69: CSU_TABLE_TIMING_MODEL<CSU_SGATE_NETLIST_TYPES>::get_cell_delay + 0x2d (db_csu)
    0x4f2eb: FSYN_TIMING_GRETA::FSYN_TIMING_GRETA + 0x16b (SYNTH_OPT)
    0x47c69: OPT_FSYN_RESYN::set_up_timing_class + 0xbd (SYNTH_OPT)
    0x4ef20: OPT_FSYN_RESYN::OPT_FSYN_RESYN + 0x2c8 (SYNTH_OPT)
    0x4661d: opt_fsyn_resyn + 0x95 (SYNTH_OPT)
    0x1cb86: FTM_ROOT_IMPL::postprocess + 0xf6 (SYNTH_FTM)
    0x1900c: FTM_ROOT_IMPL::start_normal_flow + 0x4ec (SYNTH_FTM)
    0x17f55: FTM_ROOT_IMPL::start + 0x105 (SYNTH_FTM)
    0x175b0: FTM_ROOT::start + 0xf0 (SYNTH_FTM)
    0x51645: SCL_SYN_HIER::do_tech_mapping + 0x145 (SYNTH_SCL)
    0x550b1: SCL_SYN_HIER::synthesize_with_script + 0x381 (SYNTH_SCL)
    0x55bd7: SCL_SYN_HIER::work_normal_flow + 0x737 (SYNTH_SCL)
    0x21c31: SCL_SYN_STATE::process_one_hierarchy + 0xa1 (SYNTH_SCL)
    0x2478c: SCL_SYN_STATE::synthesize_design + 0x3ec (SYNTH_SCL)
    0x2356c: scl_execute_syn + 0x9c (SYNTH_SCL)
     0x4ce2: scl_execute_normal_flow + 0x142 (SYNTH_SCL)
     0x55f4: qsyn_execute_scl + 0x254 (quartus_map)
    0x209c8: QSYN_FRAMEWORK::scl_iteration + 0x8b8 (quartus_map)
    0x134ba: QSYN_FRAMEWORK::execute_core + 0x20a (quartus_map)
    0x12cc6: QSYN_FRAMEWORK::execute + 0x476 (quartus_map)
    0x11524: qexe_do_normal + 0x1d4 (comp_qexe)
    0x16630: qexe_run + 0x3a0 (comp_qexe)
    0x17641: qexe_standard_main + 0xc1 (comp_qexe)
    0x1b208: qsyn_main + 0x558 (quartus_map)
    0x13538: msg_main_thread + 0x18 (CCL_MSG)
    0x1484e: msg_thread_wrapper + 0x6e (CCL_MSG)
    0x18210: mem_thread_wrapper + 0x70 (ccl_mem)
    0x12cf1: msg_exe_main + 0xa1 (CCL_MSG)
    0x2a408: __scrt_common_main_seh + 0x11c (quartus_map)
    0x17373: BaseThreadInitThunk + 0x13 (KERNEL32)
    0x4cc90: RtlUserThreadStart + 0x20 (ntdll)

Any insights?

I've tried cleaning the project and starting the synthesis step again, but get the same error.

We've just upgraded from 17.1 in which the project compiled fine. I've regenerated all of the IP cores out of Qsys/Platform Designer to the most recent versions.

The project is very large with a great deal of custom IP so I can't post the full project on a community forum.

[TomCarpenter]

A little bit of further information. It appears to be related to a partition containing a NIOS II processor. That is the only one that fails synthesis. Quartus just reports that it did not complete due to errors but gives no error messages - just the access violation popup.

However the exact same Qsys system generated for an Arria 10 device compiles fine. So it shouldn't be a design issue, but rather some Quartus problem.

[yanlalalala]

Hi,

Please try to use command to compile.

Fatal Error: Access Violation at 00007FF943D50950 (intel.com)

Thanks

[TomCarpenter]

Just parallel compilation being as temperamental and glitchy as usual.

Limited Quartus to use only one processor and it synthesises fine...

[TingJiangT_Intel]

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