Quartus 9.1Sp2 taking good time to generate build.

[Altera_Forum]

Our build in quartus usually takes 8-10 hours. But now its is taking ~ 20 hours with no design change. The utilization is 80 % and inclues lots of RAM. 

It takes ~ 10 hours for analysis and synthesis. It takes huge time at message "running timing driven synthesis" .   With having location constraints for RAMS or not the time taken is 20 hours.   Kindly let me know if I can improve on the build time? I am using 64 bit linux quartus and RHEL4 machine for my runs. Incremental compilation is ON.   It does not get changed even when i reduce the clock frequency to 50 Mhz for overall design.   Thanks in advance Jennyteh

[Altera_Forum]

If the initial builds were 8-10 hours, and is now 20 hours with no design change, well something changed. Specifically the analysis and synthesis couldn't have been 10 hours before as that would have been the full compile. I would certainly investigate the before/after times for synthesis. 

That being said, synthesis is the easiest to reduce with the help of Incremental Synthesis. It's just a subset of Incremental Compilation, but the partitions are only set to post-synthesis. I would recommend not doing too many partitions(say 4-8). I would also recommend doing a compile without partitions and with them and compare the area. Since all I/O in a partition are kept, logic that might have been synthesized out because you tied it off an input or didn't connect an output outside of the hierarchy will now be kept. This is all covered in the incremental compilation section of the handbook. Anyway, that should make a decent reduction in analysis and synthesis. (Most design's A&S isn't such a significant portion of compile time, which is why user's don't bother with this). Also, you can turn off Timing Driven Synthesis. I would benchmark the change in compile time, performance and area. Note that TDS usually doesn't give much better performance than just synthesized for Speed. What it does is help make the design smaller by finding portions of the design that would easily meet timing and optimizing them for area. That being said, it may not be significant and worth the compile time hit if that's where it's at. You say Incrmeental Compilation is ON, but do you have partitions? Without them, it's really not doing much, i.e. it's either going to redo the entire design or none of it, and hence it's not very incremental. I am generally leary about incremental compilation and setting partitions to post-fit. You need to floorplan your design(logiclock) and in many cases this is not trivial. Finally, really keep track of where your compile time is spent. How much is A&S. How much is TimeQuest? How much is the fitter? Open the fitter report, go to the start of messages and search on "elapsed" and you fill find many of the algorithms broken out(pre-fitter, placement, routing, physical synthesis algorithms, etc.) Without knowing where the time is spent, it's hard to know if something can be improved.