Quartus Compilation Report

[Altera_Forum]

hi, im trying to get myself familiar with altera quartus but there is a few info that i dont understand. 

 on the compilation report on this fitter summary, im not quite sure what is the total pins means. i realise on one of my project file, it use up 513/622 (82%) i wonder it is so much and what does it means.   also , on the timing analyzer summary(classic) what does worst-case tsu, worst-case tco, worst case th means?

[Altera_Forum]

The number of pins you have is indeed massive. May be you have plenty of buses in some of your modules and the fitter was left free to assign them to pins(you may have an intermediary module set as top level instead of final project top). 

The other terms are self-explanatory and there is plenty of literature on them.

[Altera_Forum]

i only have top module which have 4x4 inputs of each is std_logic_vector(15 downto 0) same goes to the outputs. Is that the reason that contributes to the massive amount of pins?

[Altera_Forum]

4 x 4 x 16 = 256 inputs 

4 x 4 x 16 = 256 outputs   total pins = 512   add clock = 513   now it makes sense if that is what you mean by 4 x 4 inputs/outputs(two dimensional)

[Altera_Forum]

ya, you are rite! thanks! 

 by the way, will it do any harm for having such a massive amount of buses? and if i were to expand my circuit design to 8x8 two dimensional inputs/outputs is that possible?

[Altera_Forum]

Your pins are inherent to your design ??? Any change -usually -requires a respin of the entire board. Anyway look at what you want and may be can do with less pins. 

 8 x 8 x 16 x2 = 2048 and exceeds your device resource. You are in very deep trouble !!!

[Altera_Forum]

if i need to perform image processing, what is the appropriate way to handle the inputs and outputs without exceeding the device resource?

[Altera_Forum]

Can't you byte-interface external to fpga then process inside fpga at higher suitable speed?

[Altera_Forum]

--- Quote Start ---  Can't you byte-interface external to fpga then process inside fpga at higher suitable speed?  --- Quote End ---    byte interface external as in how?

[Altera_Forum]

I don't know about your setup but usually in 2-D image processing engineers wouldn't flood the board with so many pins and connections equal to the number of a frame. A frame is processed inside the fpga at whatever suitable speed. 

Can you throw some light on your input/output and required processing...

[Altera_Forum]

so in that case i need to use some memory to hold the input and output then?

[Altera_Forum]

Yes you will need to play around memory and speed to get things done in time and control flow. I am sure you board mustl have a byte connection or so, no more

[Altera_Forum]

alright! thanks alot for your advice. i will try!