Quartus II Cyclone III DDR Memory problem

[Altera_Forum]

I am trying to use 32 MB DDR SDRAM in Cyclone III EP3C25F324C8. But when i compile the project, it gives me error saying 

 The DQ group with DQS pin "mem_dqs_to_and_from_the_memddr[0]" has invalid DQ group assignments  Error: The "2.5 V" I/O standard and/or the "Default" current strength on the pin "mem_dq_to_and_from_the_memddr[0]" is not supported for DDR/DDR2 external memory interfaces  Info: The combination of the I/O standard "SSTL-2 Class I" and the current strength "8mA" is a supported setting  Info: The combination of the I/O standard "SSTL-2 Class I" and the current strength "12mA" is a supported setting  Info: The combination of the I/O standard "SSTL-2 Class II" and the current strength "16mA" is a supported setting  Info: The combination of the I/O standard "SSTL-18 Class I" and the current strength "8mA" is a supported setting  Info: The combination of the I/O standard "SSTL-18 Class I" and the current strength "10mA" is a supported setting  Info: The combination of the I/O standard "SSTL-18 Class I" and the current strength "12mA" is a supported setting  Info: The combination of the I/O standard "1.8-V HSTL Class I" and the current strength "8mA" is a supported setting  Info: The combination of the I/O standard "1.8-V HSTL Class I" and the current strength "10mA" is a supported setting  Info: The combination of the I/O standard "1.8-V HSTL Class I" and the current strength "12mA" is a supported setting  Info: The combination of the I/O standard "1.8-V HSTL Class II" and the current strength "16mA" is a supported setting  Can anyone help me to solve this problem

[Altera_Forum]

Your DQ pin name looks like you are using SOPC Builder. Even when it is run through SOPC Builder, I think the DDR MegaCore MegaWizard generates a .tcl file with constraints for things like I/O standards. Make sure you've run that script or manually made the same assignments. 

 The MegaCore user guide might have instructions for running the script. You can get to the user guide through a button in the MegaCore MegaWizard GUI.  Also notice what is in the MegaCore MegaWizard dialog box when MegaCore generation completes. It will list some things you need to do that are not covered by the script.

[Altera_Forum]

I built my owm SOPC builder and added DDR SDRAM, cpu, ssram, flash, jtag-uart. I wrote my own tcl file and ran the tcl file. The pin assignments are according to the schematic.

[Altera_Forum]

You're still going to have to make pin assignments like I/O standard that are compatible with the DDR MegaCore.

[Altera_Forum]

It looks like FvM told you essentially the same thing at the end of his post at http://www.alteraforum.com/forum/showthread.php?p=7362#post7362.

[Altera_Forum]

I ran the tcl srcript and made changes in the I/O standards and the project compiled. Thanks for your help

[Altera_Forum]

I'm glad you got past your error.

[Altera_Forum]

Most DDR interfaces would use the SSTL-2 I/O standard. Is there some reason you need to use 2.5v instead?

[Altera_Forum]

I also have run into the same problem: 

Error: altmemphy pin placement was unsuccessful Error: The DQ group with DQS pin "mem_dqs_to_and_from_the_ddr_sdram" has invalid DQ group assignments Error: The "2.5 V" I/O standard and/or the "Default" current strength on the pin "mem_dm_from_the_ddr_sdram" is not supported for DDR/DDR2 external memory interfaces I'm trying to compile the standard design from the Altera Nios II Embedded Evaluation Kit, Cyclone III edition. I ran SOPC Builder, generated the design, came back to Quartus II and set the "cycloneIII_embedded_evaluation_kit_standard_sopc.v" file as the top-level file (rather than the default "cycloneIII_embedded_evaluation_kit_standard.v" which doesn't have the SOPC-based design in it). Then, as specified in the ddr and ddr2 sdram high-performance controller user guide (and echoed here in this thread), I ran the constraints file (ddr_sdram_pin_assignments.tcl) before I compiled the project. The Analysis & Synthesis phase completes Ok, but compilation fails during the Fitter phase.  Thus, I still see the error message listed above. I've checked the Assignment Editor, and all of the memory signals (such as mem_dq, mem_dqs, and mem_dm) are assigned to I/O Standard SSTL-2 Class I.  I'm not an expert with DDR SDRAM, so this message mystifies me. Should I change the I/O Standard to SSTL-2 Class II? Or is there some additional step I've overlooked?

[Altera_Forum]

It seems that not all DDR memory are assigned to the correct IO standard. Some seem to use default 2.5V standard. This should not happen with ddr_sdram_pin_assignments.tcl, but I can't see from the error message which signals are conflicting.  

 The difference between SSTL-x Class I and Class II doesn't matter in this respect, although it may important for correct operation of the design. You should expect that the design compiler selects the correct settings based on your hardware description.