Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
17268 Discussions

Quartus II IOE assignment.

Altera_Forum
Honored Contributor II
1,741 Views

Hi all 

 

Whats the easiest way to make sure Quartus II put flops in IOElement ? Example, line would be very helpful. I would rather not use "pragmars" in the source code (Verilog). 

 

Also I seems to remember only a certain type of flops (i.e. either sync/async reset/set) can be put into IOE ? Advice on that will also be appreciated. 

 

Example pin assignment file would be very useful for me as well. 

 

Thanks everyone.
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
1,052 Views

 

--- Quote Start ---  

Hi all 

 

Whats the easiest way to make sure Quartus II put flops in IOElement ? Example, line would be very helpful. I would rather not use "pragmars" in the source code (Verilog). 

 

Also I seems to remember only a certain type of flops (i.e. either sync/async reset/set) can be put into IOE ? Advice on that will also be appreciated. 

 

Example pin assignment file would be very useful for me as well. 

 

Thanks everyone. 

--- Quote End ---  

 

 

Hi, 

 

first of all you have to define FF's for your input and output signals. In the assignment editor you can specify "Fast Input Register" and "Fast Output Register" for the Input and outputs. 

 

Kind regards 

 

GPK
0 Kudos
Reply