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Quartus II Internal Error on finishing fitting

Altera_Forum
Honored Contributor II
1,293 Views

Hi All, 

 

I've posted about internal errors before, but now I am getting a different one. The code was compiling without issue until I changed an "if" condition to use a different register within the module, and now the code won't compile and generates the following error at 92% of the way through fitting. If anyone has any knowledge as to why this might be please let me know. Is re-installing the Quartus II software my only option, or is there something specific my code may be doing that could cause this? (Code snippet is also below) 

 

 

Thanks for any help! 

 

Variable definition (the first in input from a different module, the second is an output from a FIFO constructed within the module); 

 

input FIFO_Read_Rq; 

wire FIRFIFO_Rd_Empty; 

 

 

Culpable IF statement (the first condition compiles fine, the second - shown here active, does not compile at all; 

 

 

if(/*FIFO_Read_Rq == 1'b1 && */FIRFIFO_Rd_Empty == 1'b0) 

begin  

Out_Data[15:0] = PD_Data[15:0];  

end 

 

Internal Error Message; 

 

Internal Error: Sub-system: HDB, File: /quartus/h/qtl_object_cache_sys.h, Line: 711 

slice->m_locks == 0 

Stack Trace: 

0x959a0: HDB_ENUM_OPTION::get_value + 0x282a0  

0x47e96: HDB_ACTION_PT_INSTANCE::find_design_unit + 0x4f6  

0x2117: HDB_FILE_DEPENDENCIES::~HDB_FILE_DEPENDENCIES + 0x1d7  

0x1fa3: HDB_FILE_DEPENDENCIES::~HDB_FILE_DEPENDENCIES + 0x63  

0x40bb0: HDB_ACTION_PT_INSTANCE::~HDB_ACTION_PT_INSTANCE + 0x250  

0x57a5c: HDB_CHIP::reset_visited_flag + 0x33c  

0x5db48: HDB_CMP_ACTION_PT_INSTANCE::sweep_timegroups + 0xe8  

0x5db6d: HDB_CMP_ACTION_PT_INSTANCE::sweep_timegroups + 0x10d  

0x54a87: HDB_CMP_ACTION_PT_INSTANCE::close_pdb_and_clear_cache + 0x127  

0x2cbb: HUT_UTIL::restore_cap_inst_from_pdb + 0xfb  

0xa736: CSYN_EXPERT:: operator= + 0x89a6  

0x45fe4: CSYN_ENV::restore_state + 0x104  

0x2751: FSYN_ENV::restore_state + 0x31  

0x11acb: CSYN_EXPERT:: operator= + 0xfd3b  

0x6a1f: CSYN_EXPERT:: operator= + 0x4c8f  

0x4d4b6: CSYN_EXPERT::run_single_algorithm + 0x296  

0x4c340: CSYN_EXPERT::run_flow + 0xd0  

0x4b891: CSYN_EXPERT::late_fsyn_flow + 0x291  

0x48e5a: CSYN_EXPERT::do_physical_synthesis + 0x68a  

0x5b888e: VPR_QI_FACADE::vpr_qi_fsyn_fus_init_chle_lib_api + 0xfd41e  

0x2c9ad9: VPR_QI_FACADE::~VPR_QI_FACADE + 0xdad19  

0x1c5cf9: VPR_QI_FACADE::vpr_qi_get_start_and_end_progress_bar_perc_for_fsyn + 0x1b05a9  

0x1b80fd: VPR_QI_FACADE::vpr_qi_get_start_and_end_progress_bar_perc_for_fsyn + 0x1a29ad  

0x19b275: VPR_QI_FACADE::vpr_qi_get_start_and_end_progress_bar_perc_for_fsyn + 0x185b25  

0x1a2b8d: VPR_QI_FACADE::vpr_qi_get_start_and_end_progress_bar_perc_for_fsyn + 0x18d43d  

0x1c5d5b: VPR_QI_FACADE::vpr_qi_get_start_and_end_progress_bar_perc_for_fsyn + 0x1b060b  

0x1db717: VPR_QI_FACADE::vpr_qi_main + 0x27  

0x2de91: fitapi_run_vpr + 0x71  

0x46e18: FITCC_EXPERT::run_vpr + 0x138  

0x48c0f: FITCC_EXPERT:: place_and_route + 0x14f  

0x4aff1: FITCC_EXPERT::invoke_fitter + 0x711  

0x4798: fcuda_execute + 0x1f8  

0xbab9: fmain_start + 0x7f9  

0x1525: Legacy_fitter_Init + 0x4b5  

0x2618: Legacy_fitter_Init + 0x15a8  

0x2168: Legacy_fitter_Init + 0x10f8  

0xf8a6: TclInvokeStringCommand + 0xc6  

0x112a8: TclEvalObjvInternal + 0x328  

0x121b5: TclEvalEx + 0x8d5  

0x12d48: TclEvalObjEx + 0x2d8  

0x1abbd: Tcl_EvalObjCmd + 0xfd  

0x112a8: TclEvalObjvInternal + 0x328  

0x56917: TclExecuteByteCode + 0xe47  

0xa2376: TclObjInterpProcCore + 0x76  

0x112a8: TclEvalObjvInternal + 0x328  

0x56917: TclExecuteByteCode + 0xe47  

0xa2376: TclObjInterpProcCore + 0x76  

0x112a8: TclEvalObjvInternal + 0x328  

0x121b5: TclEvalEx + 0x8d5  

0x7c117: Tcl_FSEvalFileEx + 0x1d7  

0x7a626: Tcl_EvalFile + 0x36  

0xc1ff: qexe_ipc_progress_bar_name + 0x12bf  

0x11dd6: qexe_get_command_line + 0x1556  

0x150d5: qexe_run_tcl_option + 0x585  

0x1e03d: qcu_run_tcl_option + 0xb8d  

0x156ed: qexe_process_cmdline_arguments + 0x54d  

0x15851: qexe_standard_main + 0xa1  

 

 

0xa7f8: msg_exe_fini + 0x58  

0xaf3c: msg_exe_fini + 0x79c  

0x1f14: MEM_SEGMENT_INTERNAL::~MEM_SEGMENT_INTERNAL + 0x194  

0xb8bf: msg_exe_main + 0x8f  

 

 

0x1841: BaseThreadInitThunk + 0x19  

0x57508: RtlUserThreadStart + 0x20  

 

 

End-trace 

 

 

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
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Altera_Forum
Honored Contributor II
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Internal errors are usually deterministic and re-installing Quartus won't help. The fact that it occurs in the fitter doesn't help, because your code makes it through synthesis and generates something that is passed to the fitter, so there is nothing "wrong" with your HDL. What are the fitter messages around it? Maybe you can see what's occurring and maybe there's a way to get around it. For example, if Physical Synthesis is occurring, maybe you could turn it off. What happens if you try a different seed?

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