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17268 Discussions

Quartus II Internal Error

Altera_Forum
Honored Contributor II
1,740 Views

Hi, 

I'm not very experienced with FPGAs. Can some one help me with the following problem please! 

I did "Analysis an Elaboration" on my design and it was successful. 

Then I tried "Analysis and Synthesis" and I get the following error. I guess it is related to timing and .sdc file. 

Can someone give me a clue how to resolve this problem? 

 

----------------------------------------- 

Internal Error: Sub-system: SSC, File: /quartus/tsm/ssc/ssc_timing.cpp, Line: 93 !use_relaxed_slacks || (tdc_edge_slacks != 0) 

Stack Trace: 

0xf460: SSC_UTIL::compute_average_lut_delay + 0xed0  

0x10b77: SSC_UTIL::perform_timing_analysis + 0x467  

0x342ce: sutil_ssc_perform_timing_analysis + 0x1be  

0x68b6f: MAP_TESLA::set_lut_cost + 0x400f  

0x670e0: MAP_TESLA::set_lut_cost + 0x2580  

0x26d7e: FTM_ROOT_IMPL::lutmap + 0x54e  

0x24392: FTM_ROOT_IMPL::start_normal_flow + 0x152  

0x23909: FTM_ROOT_IMPL::start + 0x149  

0x23008: FTM_ROOT::start + 0x128  

0x604a3: scl_start + 0x5ab83  

0x6101d: scl_start + 0x5b6fd  

0x65113: scl_start + 0x5f7f3  

0x2ebb5: scl_start + 0x29295  

0x2f7b7: scl_start + 0x29e97  

0x2fcff: scl_start + 0x2a3df  

0x5435: scl_run_parallel_mls_script + 0xf95  

 

 

 

 

 

 

 

 

0x11fad: qexe_get_command_line + 0x1b7d  

0x14e0e: qexe_process_cmdline_arguments + 0x59e  

0x14f21: qexe_standard_main + 0xa1  

 

 

0x4ae8: msg_exe_fini + 0x58  

0x522c: msg_exe_fini + 0x79c  

0x1524: MEM_SEGMENT_INTERNAL::~MEM_SEGMENT_INTERNAL + 0x194  

0x5e0f: msg_exe_main + 0x8f  

 

 

0x159bc: BaseThreadInitThunk + 0xc  

0x2a2e0: RtlUserThreadStart + 0x20  

 

 

End-trace 

 

 

Quartus II 64-Bit Version 13.0.0 Build 156 04/24/2013 SJ Web Edition
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3 Replies
Altera_Forum
Honored Contributor II
1,028 Views

This is a crash - no idea what caused it. Try a newer version of quartus or raising a support ticket.

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Altera_Forum
Honored Contributor II
1,028 Views

 

--- Quote Start ---  

This is a crash - no idea what caused it. Try a newer version of quartus or raising a support ticket. 

--- Quote End ---  

 

 

Thank you. I did file a service request.  

But I guess it has something to do with the timing. As I was trying to do analysis and elaboration, I was getting error for my verilog.v file. Finally I resolved that problem and now I'm getting this problem. I have minimum experience with creating .sdc file.
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Altera_Forum
Honored Contributor II
1,028 Views

It could be anything - wait and see what altera suggest. Have you tried in a different version?

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