Quartus II Ripping Out Logic

Altera_Forum · ‎11-06-2014

I'm trying to understand why Quartus is ripping out my logic. I'm trying to implement a microprocessor bus interface to an ARM based part, and I kept getting notes about being unable to find my clock pins. As I dug into it, I found it was saying that my clock input wasn't driving any logic. I've stripped everything out and have it down to a dummy piece of RTL and I'm still seeing my clock ripped out.

library ieee;use ieee.std_logic_1164.all;
entity dummy is
  port
  (
    fpga_clk : in std_logic;
    fpga_rst : in std_logic;
    fpga_led_tp  : out std_logic_vector(5 downto 0)
  );
end entity dummy;
library ieee;
use ieee.numeric_std.all;
architecture rtl of dummy is
  signal sysrst     : std_logic;
  signal sysrstn    : std_logic;
  signal reset_count : integer range 0 to 20;
begin
  rst_con : process(fpga_clk)
  begin
    if ( rising_edge(fpga_clk) ) then
      if ( fpga_rst = '0' ) then
        sysrst <= '1';
        reset_count <= 0;
      else
        if ( reset_count < 20 ) then
          reset_count <= reset_count + 1;
        else
          sysrst <= '1';
        end if;
      end if;
    end if;
  end process rst_con;
  sysrstn <= not(sysrst);
  fpga_led_tp <= (others => sysrstn);
end architecture rtl;

And the RTL viewer shows the clock and all the logic as expected (see the attachment--I can't seem to get Chrome to properly operate with an embedded image).

But when I run the compilation, I end up seeing:Info (12127): Elaborating entity "dummy" for the top level hierarchy

Warning (13024): Output pins are stuck at VCC or GND

Warning (13410): Pin "fpga_led_tp[0]" is stuck at GND

Warning (13410): Pin "fpga_led_tp[1]" is stuck at GND

Warning (13410): Pin "fpga_led_tp[2]" is stuck at GND

Warning (13410): Pin "fpga_led_tp[3]" is stuck at GND

Warning (13410): Pin "fpga_led_tp[4]" is stuck at GND

Warning (13410): Pin "fpga_led_tp[5]" is stuck at GND

Info (17049): 5 registers lost all their fanouts during netlist optimizations.

Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"

Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL

Warning (21074): Design contains 2 input pin(s) that do not drive logic

Warning (15610): No output dependent on input pin "fpga_rst"

Warning (15610): No output dependent on input pin "fpga_clk"

Which doesn't make any sense at all. Clearly fpga_led_tp is NOT driven by a constant, and fpga_rst and fpga_clk ARE driving logic!

Any idea what is going on?

Attached is the full log file.

(Edit: I'm using "Quartus II 64-Bit Version 14.0.2 Build 209 9/17/2014 SJ Full Version" on Kubuntu 14.04)

Altera_Forum · ‎11-06-2014

The synthesis tool correctly determines that sysrst is only ever '1', so removes the redundant logic.

I suspect you really want the second version to go to '0' :)

If you had first simulated your design in Modelsim, you would not need to ask such a question ... hint hint :)

Cheers,

Dave

Altera_Forum · ‎11-06-2014

Doh!

A simple oversight. Ack!

Sometimes you just need a second set of eyes....