Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Quartus II waveform editor always shows output as Forcing Unknown

Altera_Forum
Honored Contributor II
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I am using altera tutorial (Simulation of Verilog Designs) example in quartus II (ver9) and I always get output as 'Forcing Unknown'. I even tried out other verilog code examples also will get Forcing Unknown output (X) only. 

Anyone know what's wrong? I suspected some setting problem but I do not know where to edit or check out. Please help.
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