Quartus : Master clock could not be derived

[qrive1]

I am working on Stratix 10 and Quartus 18.1 pro.

Im using a PLL created with the IP 'IOPLL' in order to create a 40MHz clock from a 320MHz clock input from Si5341 ("pll_40").

Normally, I don't have to define both clocks since they are respectively 'iopll_refclk' and 'iopll_outclk' and so are defined in the ip.

I have another pll, almost the same, which is creating its own clocks constraints without problem ("pll_gen").

So where is the difference and why do I have these error messages :

Warning(332087): The master clock for this clock assignment could not be derived. Clock: ip|iopll_0_n_cnt_clk was not created.

Warning(332035): No clocks found on or feeding the specified source node: ip|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll|refclk[0]

Thanks in advance,

[SreekumarR_G_Intel]

Can you please attach the design in the forum ? It will helpful to look at more in details

Thank you ,

Regards,

Sree

[qrive1]

Is this enough?

[SreekumarR_G_Intel]

Thank you for sharing the files ,

Reason I requested for the file that I assumed you already done the constraint manually and getting the this warning. Hence I am curious to know what is going on :) ..

Anyway I noticed you didnt add constraint ,Can you create .sdc file (Add to the project) and add below commands to it . Once I added , those warning went off

derive_pll_clocks -create_base_clocks

derive_clock_uncertainty

create_clock -period 10.000 -name refclk1 -waveform {0 5} [get_ports {clk_ffly0_ref}] 

Also Noticed your top module of VHDL is incomplete . (i.e) VHDL based RTL must add the component port and port mapping of those component .

Attached modified top module file for reference.

Thank you,

Regards,

Sree

[qrive1]

I think "derive_pll_clocks" command is obsolete (with quartus 18.1 pro and stratix 10)

But sorry I wasn't clear : It's just about understanding why, not about solving a concrete case.

My question is exactly on why do I have to define the clk_ffly0_ref for the pll_40 and I don't have to do it for the refclk_100 in the pll_gen. It doesn't seem logic to me.

Since all my clocks are part of a PLL, it should not be necessary to declare any clock (I mean create_clock or create generated clock commands).

Thanks in advance

[SreekumarR_G_Intel]

sorry , caught into other stuff and missed out ,

Actually i am not sure why not for the both the clock, I will raise the quires to the internal team and come back to you .

Meanwhile if you find anything similar can you let me know as well so i can learn from you.

Thank you ,

Regards,

Sree