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Valued Contributor III
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Quartus Prime 17.1 with Intel HLS Compiler issues

Hi, I have installed MS Visual Studio 2010 and Quartus Prime 17.1 with Modelsim Intel FPGA Starter Edition 10.5b to my Windows 10 computer. I am trying to run counter example in hls. Here, the output when I run build.bat -test-fpga: 

 

C:\intelFPGA\17.1\hls\examples\counter>build.bat test-fpga i++ -march=StratixV counter.cpp -o test-fpga.exe test-fpga.exe : warning LNK4088: image being generated due to /FORCE option; image may not run Run test-fpga.exe to execute the test.  

 

Then, I try to simulate running test-fpga.exe it just prints "PASSED" nothing happens. What should be the problem? 

 

Thanks.
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Valued Contributor III
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Hi, 

 

Counter.cpp have only two printf statement for the pass and fail condition, count values are not displayed. 

To see the count values introduce printf statement for seeing the count values at console. 

Example: for(unsigned int i=0; i < SIZE; ++i) { if (result != i) { printf("ERROR: Expected %u, found %u\n", i, result); pass = false;} else{ printf("Expected %u, found %u\n", i, result); } }  

You can also run test-x86-64.exe to see the result after compilation using command build.bat test-x86-64 

 

https://alteraforum.com/forum/showthread.php?t=57668 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
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Valued Contributor III
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Thank you for your response Anand. However, my point was when I ran the test-fpga.exe should not it start a simulation in modelsim?

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Valued Contributor III
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Hi, 

 

 

--- Quote Start ---  

when I ran the test-fpga.exe should not it start a simulation in modelsim? 

--- Quote End ---  

 

No,  

It should be manually done. 

 

Let me know if you need any further assistance. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
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Valued Contributor III
19 Views

Thank you, Anand. I got it. I think I misunderstood this part of the video: https://youtu.be/nybw9k7knj4?list=pl0pu5hg9ynizjbcomw4a-vsft7jyd1mli&t=1709. Executable tests the component using ModelSim simulator. For simulation results, I need to run verification\vsim.wlf manually.

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Valued Contributor III
19 Views

Hello,  

I am a beginner. I apologize for my ignorance, but could someone explain in detail the procedure to follow in order to simulate the counter in modelsim. 

I have compiled the component with: 

build test-fpga 

and that created the project folder with the 4 subfolders (I have only changed the build.bat to compile for CycloneV) 

So now I have the .proj  

From here, can someone help me with step-by-step instructions on how to run simulation. 

 

I have tried several ways but with no success. 

 

Thank you
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Valued Contributor III
19 Views

 

--- Quote Start ---  

Hello,  

I am a beginner. I apologize for my ignorance, but could someone explain in detail the procedure to follow in order to simulate the counter in modelsim. 

I have compiled the component with: 

build test-fpga 

and that created the project folder with the 4 subfolders (I have only changed the build.bat to compile for CycloneV) 

So now I have the .proj  

From here, can someone help me with step-by-step instructions on how to run simulation. 

 

I have tried several ways but with no success. 

 

Thank you 

--- Quote End ---  

 

 

Can anyone help?
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Valued Contributor III
19 Views

 

--- Quote Start ---  

Can anyone help? 

--- Quote End ---  

 

 

Can you please open new Thread/Case. 

Because present thread title and question you asked does not match, which will not help forum user. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
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Valued Contributor III
19 Views

In build.bat file you need to add -gvhdl as a compiler option to i++. 

So it should be look like  

 

i++ -march="fpgafamily" -gvhdl counter.cpp -o test-fpga.exe 

 

Then build test-fpga and run test-fpga.exe. This will create a simulation file under verification folder. 

 

 

Finally, open the verification\vsim.wlf file with Modelsim.
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Valued Contributor III
19 Views

 

--- Quote Start ---  

In build.bat file you need to add -gvhdl as a compiler option to i++. 

So it should be look like  

 

i++ -march="fpgafamily" -gvhdl counter.cpp -o test-fpga.exe 

 

Then build test-fpga and run test-fpga.exe. This will create a simulation file under verification folder. 

 

 

Finally, open the verification\vsim.wlf file with Modelsim. 

--- Quote End ---  

 

 

I have encountered an error when I did this. I have opened a new thread for this problem here: https://www.alteraforum.com/forum/showthread.php?t=58394&p=237529#post237529 

Please post your comments there.
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Valued Contributor III
19 Views

Hi,  

I want to make this counter on the 7 segment display of DE1 SoC board, my question is: How can I do this with intel HLS ?? 

Thank you 

Best Regards,  

Sarah
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Highlighted
Valued Contributor III
19 Views

 

--- Quote Start ---  

Hi, 

 

Counter.cpp have only two printf statement for the pass and fail condition, count values are not displayed. 

To see the count values introduce printf statement for seeing the count values at console. 

Example: for(unsigned int i=0; i < SIZE; ++i) { if (result != i) { printf("ERROR: Expected %u, found %u\n", i, result); pass = false;} else{ printf("Expected %u, found %u\n", i, result); } }  

You can also run test-x86-64.exe to see the result after compilation using command build.bat test-x86-64 

 

https://alteraforum.com/forum/showthread.php?t=57668 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation) 

--- Quote End ---  

 

 

Hi, 

I want to make this counter on the 7 segment display of DE1 SoC board, my question is: How can I do this with intel HLS ?? 

Thank you 

Best Regards, 

Sarah
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Highlighted
Valued Contributor III
19 Views

hi, 

how to make counter on 7 segment display de1 soc with c++ program for intel hls?? 

thanks for replying, 

best regards
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Highlighted
Beginner
19 Views

I also use CyconeV. Do you meet the LNK4088 waring?​

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