Hi,
I saw the two log files,but i still can not find the error.
Provide two files below and look forward to your reply.
Below is make_qii_design_errors.log
Info: *******************************************************************
Info: Running Quartus Prime Shell
Info: Version 22.1std.2 Build 922 07/20/2023 SC Standard Edition
Info: Copyright (C) 2023 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and any partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel FPGA IP License Agreement, or other applicable license
Info: agreement, including, without limitation, that your use is for
Info: the sole purpose of programming logic devices manufactured by
Info: Intel and sold by Intel or its authorized distributors. Please
Info: refer to the applicable agreement for further details, at
Info: https://fpgasoftware.intel.com/eula.
Info: Processing started: Sat Nov 4 22:28:17 2023
Info: Command: quartus_sh -t C:/Users/User/AppData/Local/Temp/alt9665_6029633298256525415.dir/0002_alt_mem_if_civ_ddr2_emif_0_gen/make_qii_design.tcl
Info:
Info: *************************************************************************
Info: Altera External Memory Interface IP Example Design Builder
Info:
Info: Type : Quartus Prime Project
Info: Family: Cyclone IV E
Info: Device: EP4CE55F23C8
Info:
Info: This script takes ~1 minute to execute...
Info: *************************************************************************
Info:
Info: Generating example design files...
Error (23031): Evaluation of Tcl script C:/Users/User/AppData/Local/Temp/alt9665_6029633298256525415.dir/0002_alt_mem_if_civ_ddr2_emif_0_gen/make_qii_design.tcl unsuccessful
Error: Quartus Prime Shell was unsuccessful. 1 error, 0 warnings
Error: Peak virtual memory: 4631 megabytes
Error: Processing ended: Sat Nov 4 22:29:34 2023
Error: Elapsed time: 00:01:17
Error: Total CPU time (on all processors): 00:00:22
------------------------------------------------
child process exited abnormally
while executing
"exec -ignorestderr $qsys_generate_exe_path $qsys_file --synthesis --output-directory=. --family=$family --part=$device >>& ip_generate.out"
(file "C:/Users/User/AppData/Local/Temp/alt9665_6029633298256525415.dir/0002_alt_mem_if_civ_ddr2_emif_0_gen/make_qii_design.tcl" line 92)
------------------------------------------------
And this is make_sim_design_errors
Info: *******************************************************************
Info: Running Quartus Prime Shell
Info: Version 22.1std.2 Build 922 07/20/2023 SC Standard Edition
Info: Copyright (C) 2023 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and any partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel FPGA IP License Agreement, or other applicable license
Info: agreement, including, without limitation, that your use is for
Info: the sole purpose of programming logic devices manufactured by
Info: Intel and sold by Intel or its authorized distributors. Please
Info: refer to the applicable agreement for further details, at
Info: https://fpgasoftware.intel.com/eula.
Info: Processing started: Sat Nov 4 22:29:35 2023
Info: Command: quartus_sh -t C:/Users/User/AppData/Local/Temp/alt9665_6029633298256525415.dir/0002_alt_mem_if_civ_ddr2_emif_0_gen/make_sim_design.tcl
Info:
Info: *************************************************************************
Info: Altera External Memory Interface IP Example Design Builder
Info:
Info: Type : Simulation Design
Info: Family : Cyclone IV E
Info: Language: VERILOG
Info:
Info: This script takes ~1 minute to execute...
Info: *************************************************************************
Info:
Info: Generating example design files...
Error (23031): Evaluation of Tcl script C:/Users/User/AppData/Local/Temp/alt9665_6029633298256525415.dir/0002_alt_mem_if_civ_ddr2_emif_0_gen/make_sim_design.tcl unsuccessful
Error: Quartus Prime Shell was unsuccessful. 1 error, 0 warnings
Error: Peak virtual memory: 4631 megabytes
Error: Processing ended: Sat Nov 4 22:32:10 2023
Error: Elapsed time: 00:02:35
Error: Total CPU time (on all processors): 00:00:30
------------------------------------------------
child process exited abnormally
while executing
"exec -ignorestderr $qsys_generate_exe_path $qsys_file --simulation=$lang --output-directory=. --family=$family --part=$device >>& ip_generate.out"
(file "C:/Users/User/AppData/Local/Temp/alt9665_6029633298256525415.dir/0002_alt_mem_if_civ_ddr2_emif_0_gen/make_sim_design.tcl" line 104)
------------------------------------------------
