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Hi I am new to Quartus and FPGAs. I am trying to use the Platform Designer and create a NIOS2 simple system but when I go to generate the HDL I get an error of failed to find module. I have tried different modules like memory, JTAG uart and I get the same error. What am I doing work can anyone point me in the right direction?
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Hi,
Could you try the Platform Designer Tutorial to generate HDL for Nios II processor in the link below:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/tt/tt_qsys_intro.pdf
Thanks
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Does the NIOS II need a license to work and the HDL file to generate? I followed a similar tutorial with the same results. The Platform Designer shows no errors until I click the generate HDL button then I get the error of can't find module for the system I am making.
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Hi,
May I know the information as below:
- Quartus Prime edition and version
- Os version
Thanks
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Hi,
For the Quartus Prime Lite edition is not required license file.
I had try to generate HDL for a system with with step as below:
1. New Project (in Quartus)
2. Open PLatform Designer
3. Connect the system with clock source and Avalon-MM clock crossing bridge
4. Generate HDL
It is successfully generate.
May I have the full error message for further investigate?
Thanks
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Hi,
I am not able to look into the screenshot. Could you try to attach the screenshot again?
Thanks
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Hi,
I am still not able to have the zipped attachment as seen in picture below:
You may try to attach the picture as picture below:
Thanks
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Hi,
I have tried this system connection in Quartus Prime Pro 19.3 and the system is not allowed to connect data master to on-chip memory s1 and avalon mm pipeline bridge s0. But in your picture show no error with this connection.
I had reported this issue to the developer.
Also, I had tried to used Quartus Prime Lite v18.1 to connect the system in Platform Designer as well. It does not show the error with failed to find module.
May you try to revert back to Quartus Prime Lite v18.1?
Thanks
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Hi,
Glad to hear that you have success to generate HDL in Platform Designer.
Thanks
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To solve your problem, you need to set the "Create HDL design files for synthesis" to "None" in the generation window in Platform Designer

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