Quartus Prime Pro 25.1.0 Reports Unconstrained Paths in Cyclone 10GX PCIe Hard IP

[WGao1]

Hi,

Recently I have installed Quartus Prime Pro 25.1.0 and recompiled a Cyclone 10GX design that was originally compiled in Quartus Prime Pro 20.1.0. All IP's were updated automatically in 25.1.0. The Timing Analyzer reports Illegal Clocks and Unconstrained Clocks within the PCIe Hard IP. Those errors are not reported in 20.1.0. Are they genuine errors? Can they be ignored?

Many thanks

Wei

[sstrell]

You say the IP was updated (and regenerated?) automatically.  Can you confirm that in the Upgrade IP Components dialog?

Usually when something like this happens, the easiest thing to do is just recreate the IP with the same parameters as you used originally.

[WGao1]

The upgraded IP Components in version 15.1.0 -

Before that, the dialog in version 20.1.0 is -

[WGao1]

Typo. The first image is for version 25.1.0. All IPs are regenerated.

[sstrell]

Check the .sdc files being included in the project in the Timing Analyzer settings.  Maybe it's using the old .sdc files instead of new ones generated when the IP was regenerated.

[WGao1]

I have already checked the .sdc files being included in the project in the Timing Analyzer settings and no issues are found. I also removed the IP from the project, deleted the generated IP folder within the project directory and then generated the IP from scratch. The errors are still there.

I suspect there might be errors in the generated .sdc files. The compilation flow shows a green tick before the Timing Analyzer. This indicates the design has passed the Timing Analyzer. I will compare the new sdc file with the old one and see if I can find anything.

[sstrell]

No the green checkmark doesn't mean that the TA met all timing.  It just means the TA completed its run.

[WGao1]

After digging a bit more, I have found that the xcvr fpll within the PCIe IP is missing after synthesis. Therefore no clocks are generated for the PCIe IP.

This is caused by Quartus failing to identify the architecture in the generated file "PCIE_IP_altera_pcie_a10_hip_altera_xcvr_fpll_a10_2020_tg4rxbi.vhd". The warning messages are -

There are no errors in this file. It is identical to the equivalent file generated in version 20.1.0.

This looks like a bug in version 25.1.0. It might be related to the long entity name.

[RongYuan]

My suggestion to you is to rebuild your project under Q25.1. If your project was built based on a generated example design by Q20.1, please regenerate that under Q25.1 then add your own IPs to complete your project.

Regards,

Rong