Quartus Prime20.1 can't compile systemverilog syntax

[xxerexxaa]

我在使用modsim编译成功并且成功仿真以后想使用quartus烧录至FPGA上发现许多类似于class 和数学函数的使用在quartus里无法编译。

我已经修改了quartus prime 20.1 的编译器为SystemVerilog但是还是无法编译class。请问有人遇到类似的情况吗？

据我所知可能是软件本身的问题，但是我的导师希望我最好还是使用quartus，所以请问有什么比较好的不改动代码的方案吗？

After compiling and simulating successfully with Modsim and trying to apply to FPGA with quartus, I found that ‘class’ and some maths functions cannot be compiled with quartus.

I have changed the compiler of quartus prime 20.1 to SystemVerilog but it still doesn't compile the classes. Has anyone else encountered a similar situation?

As far as I know it could be a problem with the software itself, but my tutor wants me to use quartus preferably, so is there a better solution that doesn't change the code?

[sstrell]

It might help to post the code and the exact errors you are getting.

[xxerexxaa]

Here is my code:

class iTreeNode;
NodeType ntype;
class ExNode;
int size;

function new();
size = 0; // 设置默认值
endfunction

endclass
class InNode;
iTreeNode left;
iTreeNode right;
int splitAtt;
int splitValue;
function new();
splitAtt = 0; // 设置默认值
splitValue = 0; // 设置默认值
endfunction
endclass
ExNode exNode;
InNode inNode;
function new();
// 初始化联合体成员
exNode = new;
inNode = new;
ntype = EXTERNAL_NODE; // 设置默认值
endfunction
endclass

I use classes because I need nested definition. These codes can be compiled and run successfully in Modelsim. I guess maybe the Quartus dosent support the systemverilog in some aspects.

[FvM]

Hi,

System Verilog synthesis support is specified in Quartus help. Section 8 Classes isn't supported at all.

Your math functions are possibly not synthesizable, e.g. ieee.math_real functions.

[xxerexxaa]

请问有没有办法能让quartus获得支持或者使用能适配SystemVerilog的软件呢？

Is there any way to get support from quartus or to use other softwares that can be adapted to SystemVerilog?

[FvM]

Hi,
I don't think it's a matter of the tool. Dynamic data and code definition can't be mapped to logic hardware. Nested (recursive) definitions can be used in generate constructs, but they are translated to parallel logic at compile time. If the recursion count isn't limited somehow, the construct isn't synthesizable.

[ShengN_Intel]

Hi,

Check this link https://www.doulos.com/knowhow/systemverilog/systemverilog-tutorials/systemverilog-classes-tutorial/ and this link https://verificationguide.com/systemverilog/systemverilog-class/, SystemVerilog introduces classes as the foundation of the testbench automation language. That's why classes can be used in simulator but not in compiler tool like Quartus.

Thanks,

Best Regards,

Sheng

[xxerexxaa]

Thank you!

Dose it mean that I have to change my code if I want to implement the algoritm to the FPGA? If yes, can recursive functions be used in the compiler tools?

[FvM]

Hi,
I believe I already gave the answer. See also https://stackoverflow.com/questions/70615674/are-recursive-functions-in-verilog-synthesizable

[ShengN_Intel]

Hi,

Yes, recursive functions can be used in the compiler tools. But just a heads up, if you use the recursive functions like the way below (example):

module factorial_fail (input [7:0] ip, output reg [7:0] we);

function automatic [7:0] factorial;

input [7:0] i_Num;

begin

if (i_Num == 1)

factorial = 1;

else factorial = i_Num * factorial(i_Num-1); end endfunction

always @ ip

begin we = factorial(ip); end

endmodule

You probably will get this Error(14408): Verilog HDL error at factorial_fail.sv(3): stack overflow on recursion via factorial, limit of 900 has exceeded 

So in order to pass the synthesis for recursive functions, have to implement the module with input values to the recursive function as follows:

module factorial (input [7:0] ip, output reg [7:0] we);

function [7:0] factorial1 (input [7:0] i_Num);

if (i_Num == 1)

factorial1 = 1;

else factorial1 = i_Num * factorial1(i_Num-1); endfunction

assign we = factorial1(8'd4);

endmodule

Thanks,

Best Regards,

Sheng

[ShengN_Intel]

Hi,

Any further concern on this thread?

Thanks,

Best Regards,

Sheng