Quartus Pro 22.2 SystemVerilog: argument of size should be an identifier

[alexislms]

  .DATA_WIDTH (  $size({2'b0, 2'b0, 2'b0, 4'b0})  )

Quartus issues an error at Design Analysis

Error(16845): Verilog HDL error at xxx.sv(270): argument of size should be an identifier

It shouldn't be an error, it's allowed by the SV's specs.

[ShengN_Intel]

Hi,

Probably need to do something like below for example:

byte   Dynamic_array[4] = {2'b0, 2'b0, 2'b0, 4'b0};

...

.DATA_WIDTH ( $size(Dynamic_array) )

Best Regards,

Sheng

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.

[alexislms]

Your example is wrong.

Please report the bug to the Quartus' dev team.

Regards,

[ShengN_Intel]

Hi,

Check this,

An identifier in Verilog and SystemVerilog is the user-specified name of some object, such as the name of a module, wire, variable, or function.

Therefore, I generally believe that you have to give a identifier to the array before $size it.

Check this http://courses.eees.dei.unibo.it/LABMPHSENG/wp-content/uploads/2016/02/SystemVerilog_3.1a.pdf (page 351)

Check this also https://stackoverflow.com/questions/33653958/how-to-get-the-number-of-elements-in-an-array-in-systemverilog

Besides, I further test with other synthesis tool and getting the error. So I don't think this is a bug. Check the image attached.

Thanks,

Best Regards,

Sheng

[alexislms]

Does the specs of your link has anything to do with Quartus? Does QP follow these specs? Please provide an official Intel link or reference to it.

Interesting, I do not get the error with Questa https://www.edaplayground.com/x/8yaS

And I do not get the error with Vivado 2021.2 using a more complication expression.

Please refer to the actual SV specs: IEEE 1800-2017 20.7 Array query functions.

array_expression, data_type are allowed. array_expression is expression. And it looks like expression can be a concatenation operator.

I tested with $bits() and Quartus doesn't seem to complain, that's very strange since all these functions have the same definition in the specs.

Nevertheless, I might be wrong but I'd need more convincing arguments.

Regards,

[ShengN_Intel · Accepted solution]

Hi,

Check this https://www.intel.com/content/www/us/en/docs/programmable/683236/22-2/verilog-and-systemverilog-synthesis-support.html so latest SystemVerilog supported is SystemVerilog-2012. Then can refer to IEEE Standard 1800-2012 check here http://www.ece.uah.edu/~gaede/cpe526/2012%20System%20Verilog%20Language%20Reference%20Manual.pdf (page 604) under section 20.7 Array querying functions. You can see array_identifier is mentioned. There are some examples under that section as well for your reference.

This code can be synthesized in simulator. I tested in Questa Starter Edition with no problem. So means this is something supported in testbench. If so should be no problem too as testbench normally is not included in Quartus tool for compilation. Vivado 2021.2 still fails to synthesize $size but able to synthesize $bits. Check the images attached.

Thanks,

Best Regards,

Sheng

[alexislms]

Considering IEEE1800-2012, now it explains why $bits (defined with $size in 2017's) works and not $size.

The fact Vivado shows an error for this simple case doesn't mean it isn't or shouldn't be supported.

None of $size and $bits are synthetizable. $bits is evaluated at the elaboration, not synthesized.

You can close the issue, thank you for the more convincing arguments.

[ShengN_Intel]

Sure. Thanks for your knowledge sharing. I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.