seed -> how to get same SOF for each compilation run?

[amildm]

Hi All,

Each time when I compile the design, I'm getting the different SOF files even I don't change anything neither in my Design nor in QSF... the resulting SOF will be different...

Should I freeze the seed (use the same one) for each compilation, so will the resulting SOF's be the same?

So, how can I freeze the seed?

Thank you!

[ak6dn]

The SOF will differ, because it contains a compilation time stamp.

Read this:  https://www.intel.com/content/www/us/en/support/programmable/articles/000080266.html

You can put this line in your project .qsf file to fix the seed value:

set_global_assignment -name SEED 42

[amildm]

thanks for the valuable info!

How can I know the seed, which was used for the each compilation?

If I'll set the SEED as you mentioned

set_global_assignment -name SEED 42

and will not change neither RTL nor QSF (constraints), will I be guaranteed that the final Netlist, Route and Timing be same after each project compilation (with the same SEED)?

How can I read the SOF/JIC timestamps using the System Console?

[ak6dn]

The .fit.rpt file in your design directory lists what seed value was used for the design.

I have found that I can recompile over and over again, deleting all generated files and databases, and if I don't change any source files I end up with exactly the same FPGA .pof file. As indicated previously the .sof file my change as it has an embedded timestamp.

I don't know about displaying the timestamp in a .sof file, never tried to do that. The Windows maintained file date was sufficient for me.

[amildm]

1) I'm not using the POF files (they are manly for the MAX devices). For Cyclone 10 devices I'm using the JIC files, which are generated from the SOF files.

So, do the JIC files contain be the same timestamps as SOF? Will be the JIC files the same while using the same SEED. 

2) As for the System Console, I'd wonder to know how I can check the timestamp if it's a part of JIC.

3) Anyway, I'd like to receive a response from an Intel's employee whether I'm guaranteed that the compiled logic be exactly the same when using the SAME SEED for the DIFFERENT COMPILATIONS. I mean exactly the same LOGIC used, SAME ROUTE and SAME TIMING REPORTS. 

Thank you!

[ShengN_Intel]

Hi,

May I know any further concerns or final thoughts?

Thank you.

Sheng

[amildm]

1) I'm not using the POF files (they are manly for the MAX devices). For Cyclone 10 devices I'm using the JIC files, which are generated from the SOF files.

So, do the JIC files contain be the same timestamps as SOF? Will be the JIC files the same while using the same SEED. 

2) As for the System Console, I'd wonder to know how I can check the timestamp if it's a part of JIC.

3) Anyway, I'd like to receive a response from an Intel's employee whether I'm guaranteedthat the compiled logic be exactly the same when using the SAME SEED for the DIFFERENT COMPILATIONS. I mean exactly the same LOGIC used, SAME ROUTE and SAME TIMING REPORTS. 

Thank you!

[amildm]

1) I'm not using the POF files (they are manly for the MAX devices). For Cyclone 10 devices I'm using the JIC files, which are generated from the SOF files.

So, do the JIC files contain be the same timestamps as SOF? Will be the JIC files the same while using the same SEED. 

2) As for the System Console, I'd wonder to know how I can check the timestamp if it's a part of JIC.

3) Anyway, I'd like to receive a response from an Intel's employee whether I'm guaranteedthat the compiled logic be exactly the same when using the SAME SEED for the DIFFERENT COMPILATIONS. I mean exactly the same LOGIC used, SAME ROUTE and SAME TIMING REPORTS. 

Thank you!

[ak6dn · Accepted solution]

The source files drive the logic generation / mapping phases.

So if you compile with the exact same sources, the logic produced will be exactly the same.

The SEED value only drives the fitter.

Different SEED values will produce different placements of the exact same logic.

So if you don't change the source files, the logic will be the same.

If you don't change the seed, the placement will be the same.

[amildm]

So what are the "pseudo_seed", which a see in the *.syn.rpt ?

-----------------------------------------------------------------------------------

hssi_10g_tx_pcs_pseudo_seed_a ; 288230376151711743 ; String ;
hssi_10g_tx_pcs_pseudo_seed_b ; 288230376151711743 ; String ;

hssi_10g_tx_pcs_pseudo_seed_a ; 1111111111111111111111111111111111111111111111111111111111 ; Unsigned Binary ;
hssi_10g_tx_pcs_pseudo_seed_b ; 1111111111111111111111111111111111111111111111111111111111 ; Unsigned Binary ;
-----------------------------------------------------------------------------------

[ak6dn]

Well, that is just a string seed that is part of the name of a variable in some source code.

Nothing to do with the quartus parameter named SEED.

[amildm]

If I don't constrain SEED, it always set to '1' - default value...

What cases the Fitter changes the SEED value or this never happens?

In case of the fitting problems (e.g. Timing Closure), is there a sense to randomize the SEED? What values (range of values) could it be set to?

When Fitter changes its SEED (if ever)?

[ShengN_Intel]

Hi,

I generated two sof files from same design then convert them to two hex files and compare side by side using diff tool.

Different seed: There are much differences between both the files up to thousand changes.

Same global seed: There are totally no differences between both the files with zero changes.

So should be the same for jic files and no problem if you stick with same global seed. I don't think you can check the timestamp of JIC file. Thank you.

Best Regards,

Sheng

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.

[amildm]

OK... I've checked the report files... The SEED is located in the *.fit.rpt and *.syn.rpt  files.

-----------------------------------------------------------------

From the *.fit.rpt file:

Fitter Initial Placement Seed : 1

But this is a seed for the FITTER ONLY (am I wrong?)

-----------------------------------------------------------------

But in the *.syn.rpt, there are many other seeds (see below)

So, which one should I choose for putting it to my QSF as a global SEED? Should I put all of these seeds (for Fitter and also for Synthesizer) in order to receive the same compilation results?

Anyway, from *.syn.rpt, It seems that each IP was synthesized with its own SEED, but where is the SEED which has been used for synthesizing the Glue Logic?

--------------------------------------------------------------------------------

From *.syn.rpt file:

C:\Projects\barracuda\ASIC\TX\synt\quartus\output_files\barracuda_tx_top.syn.rpt(10790): ; hssi_10g_tx_pcs_pseudo_seed_a ; 288230376151711743 ; String ;
C:\Projects\barracuda\ASIC\TX\synt\quartus\output_files\barracuda_tx_top.syn.rpt(10791): ; hssi_10g_tx_pcs_pseudo_seed_b ; 288230376151711743 ; String ;
C:\Projects\barracuda\ASIC\TX\synt\quartus\output_files\barracuda_tx_top.syn.rpt(11644): ; hssi_10g_tx_pcs_pseudo_seed_a ; 1111111111111111111111111111111111111111111111111111111111 ; Unsigned Binary ;
C:\Projects\barracuda\ASIC\TX\synt\quartus\output_files\barracuda_tx_top.syn.rpt(11645): ; hssi_10g_tx_pcs_pseudo_seed_b ; 1111111111111111111111111111111111111111111111111111111111 ; Unsigned Binary ;
C:\Projects\barracuda\ASIC\TX\synt\quartus\output_files\barracuda_tx_top.syn.rpt(12450): ; hssi_10g_tx_pcs_pseudo_seed_a ; 1111111111111111111111111111111111111111111111111111111111 ; Unsigned Binary ;
C:\Projects\barracuda\ASIC\TX\synt\quartus\output_files\barracuda_tx_top.syn.rpt(12451): ; hssi_10g_tx_pcs_pseudo_seed_b ; 1111111111111111111111111111111111111111111111111111111111 ; Unsigned Binary ;
C:\Projects\barracuda\ASIC\TX\synt\quartus\output_files\barracuda_tx_top.syn.rpt(13263): ; hssi_10g_tx_pcs_pseudo_seed_a ; 1111111111111111111111111111111111111111111111111111111111 ; Unsigned Binary ;
C:\Projects\barracuda\ASIC\TX\synt\quartus\output_files\barracuda_tx_top.syn.rpt(13264): ; hssi_10g_tx_pcs_pseudo_seed_b ; 1111111111111111111111111111111111111111111111111111111111 ; Unsigned Binary ;
C:\Projects\barracuda\ASIC\TX\synt\quartus\output_files\barracuda_tx_top.syn.rpt(14090): ; hssi_10g_tx_pcs_pseudo_seed_a ; 1111111111111111111111111111111111111111111111111111111111 ; Unsigned Binary ;

[ShengN_Intel]

Let me know if any further concerns or considerations.