Quartus Programmer long programming time when ISP clamp feature is used

[andi6510]

Hi,

I am using an MAX10 8k FPGA. Programming that device with a pof-file usually takes a few seconds. Now I tried to use the ISP clamp feature to force one of the pins to a known level during programming. Since I did this, the programming time increased dramatically and is now in the range of minutes. Programming still works fine - it's just much slower than before.

Is that normal?

Can I do something against it?

Any suggestions?

Andi

[Vicky1]

Hi Andi,

Can you please provide the following details so that we can replicate the issue?

1. Quartus Edition & Version
2. Development/Evaluation Kit used
3. Any IP used in design

Have you taken care of all the steps given in following link,

https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/an/an630.pdf

Best Regards

Vikas Jathar 

(This message was posted on behalf of Intel Corporation)

[andi6510]

Hi @vikasx.jatharX​ ,

1. We are using Quartus 15.1 Web Edition to make the POF files.
2. It is our own design, not a dev-kit. The 10M08 FPGA is connected to a EPM7032 CPLD in one JTAG chain
3. We use a lot of the (free) IP to access most of the FPGA features. But I cannot detail everything here in an open forum. I do not believe that this is relevant because the problem does not occur in user mode.
4. Yes, I am aware of that application note you have linked to and I think I followed it in every detail.

Some more observations:

For the Quartus Programmer I tried 15.1 and also 18.1 - no change in behaviour.

Programming time for both CPLD and FPGA is...

without ISP clamp: 15-20 seconds

with ISP clamp: 130-150 seconds

With ISP clamp it always does a verify, regardless if i put a tick to the verify check boxes or not.

When you add an isp file in the programmer, it always does ISP clamp, regardless if I put a tick to the ISP clamp checkboxes or not.

To enable ISP clamp I tried the following methods:

1. Adding ISP file in the programmer. In this file exactly one pin is forced to HIGH, the others are left untouched.
2. Adding the ISP-clamp property to the pin in the assignment editor in Quartus and re-generate the POF file.

Both have exactly the same behaviour.

But maybe we should start one step before: The reason for ISP clamp is, that I am using it as a workaround for another problem. I would not have to use the ISP clamp feature at all, when the "weak pull up"-feature would be working in programming mode.

But this is also kind of buggy:

I have set the tick mark at "enable weak pull up" in the ICB settings when I generated the POF file. It seems that the weak pullup is active with an empty, unconfigured device. But when I start programming the inernal flash, the pins appear to change to tristate mode. This is what is causing the my trouble. So I tried to use ISP clamp to force the relevant pin to high. But with a weak pullup that would also be fine.

So the question is: Can I use weak pullup when I program the internal flash?

Andi