Quartus QSYS in QSF keeps generating verilog (but i need VHDL)

[Altera_Forum]

Hi! 

 First of all, the question: Is there any way to tell quartus (not qsys!) to generate VHDL(and not verilog) for a qsys system?  Now the details: I've added a QSYS file to my Quartus Settings File (QSF). After that, quartus does elaborate the qsys file and generate the output in <myProjectFolder>/db/ip/*.  set_global_assignment -name QSYS_FILE ../../some/path/to/NiosSystem.qsys  When i use the qsys gui to generate the synthesis output, i can choose between verilog and VHDL, i need to choose VHDL to get round this quartus bug: https://www.altera.com/support/support-resources/knowledge-base/solutions/rd05212011_256.html  The qsys gui does respect this setting which is also saved to the qsys file:  <parameter name="hdlLanguage" value="VHDL" />  When i run a quartus compile flow from the quartus gui, this setting is not respected. I endup with verilog HDL files which i can't use (without further processing) for synthesis.  Thx!

[Altera_Forum]

Try Assignments -> Settings -> IP Settings and change it to VHDL. I am working on a design where this isn't working, but I think there's another layer of complication that makes this different. Please post if this works. Thanks.

[Altera_Forum]

Hi Rysc! 

I'm working with QuartusII 13.1 and this option is not available there. I guess you're using QuartusII 14.0 or 14.1.

[Altera_Forum]

Hello, 

 Do you have the .qsys file or the qip file in your quartus project? I have the .qip file in mine and only generate the verilog code from inside the qsys tool. When I compile the project the code does not get regenerated.  The following is from the Quartus handbook volume 1 section 5 "If you want file generation to occur as part of the Quartus II software's compilation, you should include the .qsys file in your Quartus II project. If you want to manually control file generation outside of the Quartus II software, you should include the .qip file in your Quartus II project."  Kevin

[Altera_Forum]

Yes, Q14.1 definitely has it.

[Altera_Forum]

Two questions: 

 - can you confirm that this is a qsf setting or does this endup in some sort of quartus registry setting? If it's the latter, it's quite useless because you can't easily share this with collegues and furthermore if you're doing automated builds (headless pc), you're lost.  - i guess there's no way to force vhdl in 13.1?

[Altera_Forum]

Hi someusername, 

 It is recommended for you to try using the latest Quartus II version to get the updated and enhanced feature. Quartus II 15.0 was released early May this year. Probably you could give it a try.

[Altera_Forum]

I think that the simulation now also support mix language for Q15.0, perhaps you can give it a try