Quartus Web Edition 7.1 Schematic Symbol Error

[Altera_Forum]

Hi, 

 I created a module in Verilog that I am including in a schematic as a symbol. The module has bus inputs called:  input wire [23:0] ch1, input wire [23:0] ch10, input wire [23:0] ch11, etc. up to ch16  it also has inputs called input wire ch1_U input wire ch1_V  I get this error when trying to compile the schematic with the included symbol.  Error: Illegal name "ch119" -- pin name already exists Error: Illegal name "ch118" -- pin name already exists Error: Illegal name "ch117" -- pin name already exists Error: Illegal name "ch116" -- pin name already exists Error: Illegal name "ch115" -- pin name already exists Error: Illegal name "ch114" -- pin name already exists Error: Illegal name "ch113" -- pin name already exists Error: Illegal name "ch112" -- pin name already exists Error: Illegal name "ch111" -- pin name already exists Error: Illegal name "ch110" -- pin name already exists Error: Illegal name "ch123" -- pin name already exists Error: Illegal name "ch122" -- pin name already exists Error: Illegal name "ch121" -- pin name already exists Error: Illegal name "ch120" -- pin name already exists  This was not a problem when I had only   input wire [23:0] ch1-ch8.  Does Quartus use more than three characters for their pin names? It appears like the ch1 is aliasing with ch10, etc.  Thanks for any help.  RAUL

[Altera_Forum]

Nope, 

 You must think like a computer. It is doing exactly as you ask.  I will space thinkgs out a little to help you see it better. ch1 19 looks just like ch11 9  If you rename your inputs to something like; ch1bit ch2bit ... ch11bit etc  you will get what you want.  It is always a risk to name a signal with a number if you are going to vectorize it. Avatar.

[Altera_Forum]

Thank you, very good point, I think it is a bug, though. 

 I wrote a wrapper to my module with the first three characters being different for ch1 and ch11. The Quartus schematic tool is so far the only tool that has had a problem with using ch1[23:0] and ch11[23:0]. ModelSim is OK, even Quartus Verilog Synthesis is OK.  RAUL