simulation problems

[Altera_Forum]

Ok this is really beginning to really tick me off. I am losing patience with quartus 2. Here is why: 

 This may have to do with my ignorance.  Whenever I create a simulation of lets say something like a dlatch, the input and output waveforms are NOT ALIGNED! I know that there is lag caused by the chip. Is there a real method to align them? because I can't!  for a simple S/R NAND latch the end time of 200 us and count every 20 us worked perfectly.  But for a 4bit dlatch, this is really bugging me. I don't want to play the guessing game for end time and count timing. Please tell me what is the method to align the input and output waveforms in the simulation. I am dying to know.  Just because of this, I want to take quartus and throw it out, but i can't because my college will test me on this software.  HELP! Thank you. I am very desperate.

[Altera_Forum]

I don't know whether your simulation issue is a matter of whether you are doing the simulation correctly (for example, doing functional simulation versus timing simulation to get what you are looking for). However, there are issues with latches in particular that might affect simulation of them. 

 Latches or any other combinational feedback loop are strongly discouraged in FPGA and CPLD designs. The timing analysis of combinational feedback loops creates special challenges for both the Fitter and Classic Timing Analyzer. (I don't know whether TimeQuest added a more PrimeTime-like analysis for this.)  I realize that you might be using latches in a Quartus design because you were told to for your class, but for real designs use latches only if there is not a good synchronous-design solution.  If you do use latches, carefully read Quartus handbook Volume 1, Section II, Chapter 6: Recommended HDL Coding Styles. Look at the section "Coding Guidelines for Registers and Latches --> Latches".

[Altera_Forum]

Thank you for your input. 

 Basically in the timing simulation I want to eliminate the simulated propagation delay. So that the waveforms of the output and input are in-line.  A tutorial suggests that I put the end time to 100 micro seconds and the count every timing to 10.24 micro seconds which works for simple logic gates. I want to know if there is a real method in doing this.

[Altera_Forum]

In the Assignments/Settings menu, change your simulation from Timing to Functional. Then you'll need to generate a functional netlist (process menu) before doing you simulation.

[Altera_Forum]

I'm having trouble understanding what you are actually doing given how you described it. 

 I don't know what you mean by "count every timing to 10.24 micro seconds". The only things I can think of that you might mean are a clock period for a registered portion of your design or the grid size for the simulation, neither of which will affect the delays shown through combinational logic in a timing simulation.  You said, "Basically in the timing simulation I want to eliminate the simulated propagation delay." A timing simulation will always show the device propagation delays. Any combinational logic function will always have the delay through a LUT or CPLD macrocell. You need to do a functional simulation (as in std_logic's post) to have no delay between the input and output of a logic function.  Make sure you are looking at what you think you are looking at for the "simple logic gates", which I think you are saying appear to have zero propagation delay. One logic gate like a NAND feeding another logic gate in your source file might be combined together into a single LUT/macrocell during synthesis. For a functional simulation, you can see the output of each logic gate separately with their transitions at the same time. If you are doing a timing simulation, though, you can see only the output of the LUT/macrocell no matter how much source-file logic is in that LUT/macrocell; the intermediate logic gate output nodes won't exist for the timing simulation. If you really can see each logic gate output separately in a timing simulation, then each gate must be in its own LUT/macrocell, but that means each gate is going to have some delay.  When you think you have zero delay for "simple logic gates" but nonzero delay for a latch, could you just be zoomed out far enough that you don't see the small delay for the logic gates? You mention timescales in microseconds. If you are zoomed out far enough to see multiple microseconds, then the nonzero delay through each LUT/macrocell will look like zero. Zoom in enough so that you can see what is happening at the scale of nanoseconds.  If you are using a repetitive signal pattern with input transitions separated by times on the order of nanoseconds, you could think you are seeing zero delay when you are actually seeing the delay from the input transition from one cycle of the repetitive input signal just happen to cause an output transition right about the same time as the input transition for a later cycle. When the input transitions are closely separated compared to the device propagation delays, it can be hard to tell which input transition caused which output transition.  If you did not follow the latch coding guidelines I referred you to or if you created your latch with logic gates in a schematic, you might have gotten a result that Analysis & Synthesis did not report as a safe latch. In that case, strange things can happen to the latch output in a timing simulation and in real hardware. You need to zoom in to the scale of nanoseconds to see whether the latch output has clean transitions without glitches or oscillations. More important, you need to make sure the Analysis & Synthesis report says the latch is safe. Refer to the Quartus handbook to see how this is reported.

[Altera_Forum]

Thank you very much Brad. You've actually answered my question with your comprehensive post. 

 "When you think you have zero delay for "simple logic gates" but nonzero delay for a latch, could you just be zoomed out far enough that you don't see the small delay for the logic gates? You mention timescales in microseconds. If you are zoomed out far enough to see multiple microseconds, then the nonzero delay through each LUT/macrocell will look like zero. Zoom in enough so that you can see what is happening at the scale of nanoseconds."  This paragraph details on how to hide the propagation delay in a timing simulation, so I don't have to go to functional.  This is what I was talking about.   Also thank you very much for your insight as well on the using of latches and other info. I wouldn't have known this. Definitely made me stronger in knowledge about CPLDs and latches.  I will definitely read that guide.