When you build an FPGA design Quartus generates some sort of database in the “db” and “incremental_db” folders. I was under the impression that following builds make use of this database and possibly produce better results (timing and/or shorter build time). This is based on observations my colleagues and I made. I’m pretty sure that I’ve build the exact same design sources two times in a row and the second build had slightly better timing (or at least different timing) than the first build. I have now tried to reproduce these observations, but failed doing so. I always get the exact same result, independent of the compilation database. Were we all imagining things, or did this change with some Quartus version, or is it some special setting? I’m not talking about the “Rapid Recompile” feature, I’m always doing a full compilation.
