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Verilog include file not found using 12.1sp1 Qsys (quartus_map) when opening .qsys

Honored Contributor II


About a month ago, I started porting a design to Quartus 12.1 sp1 to Qsys from Quartus 9.0 SOPC. Everthing ported file and I was able to generate my Qsys file. Then mysteriously on Friday, my Qsys project will not open properly right after I got a message saying my temp license was expired. No problem though, I verified that my licenses are in place and working.  


I start Qsys, it imports and finds all the available components. Then I select my syscore.qsys file to open. During the opening process it seems o be running quartus_map command which fails. Again prior to friday it loaded the file and generated properly. 


In my io_i2c.v file, I have a line 

'include "math.vh" 

I can see the file being included in the quaruts_map.exe command but then it says it can not find it. 

If I change the path to a relative path it works OK "../../../math.vh" but I have to keep my code base backward compatible and would rather not change the code.  


It is curious, it was working no problem. 

It says it is running Quaruts II 32-bit Generate HDL interface but I started it from my 64-bit machine? 

Could the set ALTERA_HW_TCL_KEEP_TEMP_FILES cause a problem? I don't even know where this is set. 

How does quartus_map use the various libarary and IP paths?  


Error: System.: set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files 

Error: System.: Command: C:/altera/12.1sp1/quartus/bin/quartus_map.exe not_a_project --generate_hdl_interface=C:/DESIGN_SANDBOX/rda/embedded/libs/hdl/control/io_i2c.v --source=C:/DESIGN_SANDBOX/rda/embedded/include/math.vh --source=C:/DESIGN_SANDBOX/rda/embedded/libs/hdl/control/io_i2c.v --set=HDL_INTERFACE_OUTPUT_PATH=C:/Users/jgs/AppData/Local/Temp/alt5854_6595215683943485522.dir/0003_sopcqmap/ --ini=disable_check_quartus_compatibility_qsys_only=on 

Error: System.: ******************************************************************* 

Error: System.: Running Quartus II 32-bit Generate HDL Interface 

Error: System.: Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version 


Error: System.: Command: quartus_map not_a_project --generate_hdl_interface=C:/DESIGN_SANDBOX/rda/embedded/libs/hdl/control/io_i2c.v --source=C:/DESIGN_SANDBOX/rda/embedded/include/math.vh --source=C:/DESIGN_SANDBOX/rda/embedded/libs/hdl/control/io_i2c.v --set=HDL_INTERFACE_OUTPUT_PATH=C:/Users/jgs/AppData/Local/Temp/alt5854_6595215683943485522.dir/0003_sopcqmap/ --ini=disable_check_quartus_compatibility_qsys_only=on 

Error: System.: Verilog HDL File I/O error at io_i2c.v(47): can't open Verilog Design File "math.vh" File: /design_sandbox/rda/embedded/libs/hdl/control/io_i2c.v Line: 47 

Error: System.: Ignored design unit "io_i2c" at io_i2c.v(26) due to previous errors File: /design_sandbox/rda/embedded/libs/hdl/control/io_i2c.v Line: 26 


My original _hw.tcl file had from 9.0 efforts 

add_file ../../../include/math.vh {SYNTHESIS SIMULATION} 


To try and fix the issue I have added the following to my _hw.tcl file but does not seem to help. I can see the map executable including the two files as source but it seems to have trouble connecting the include statement to the --source option. 


set_fileset_property QUARTUS_SYNTH TOP_LEVEL io_i2c 


add_fileset_file io_i2c.v VERILOG PATH ../../../libs/hdl/control/io_i2c.v 

add_fileset_file math.vh OTHER PATH ../../../include/math.vh 

add_fileset SIM_VERILOG SIM_VERILOG "" "" 


add_fileset_file io_i2c.v VERILOG PATH ../../../libs/hdl/control/io_i2c.v 

add_fileset_file math.vh OTHER PATH ../../../include/math.vh 


This does not help? 


I found a similar post about Quartus 10.0 but no one responded to it?
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2 Replies
Honored Contributor II

I solved this by adding the path to the .vh file to the Project Libraries under Settings.