Quartus compilation warnings

[Altera_Forum]

When I compile a Quartus project, with a nios system, I always have a lot of warnings like the following ones. 

I've never had any problem with the designs; everything works perfectly. However I wonder if these warnings are normal or if I have some problem in project settings.  Warning (10542): VHDL Variable Declaration warning at altera_europa_support_lib.vhd(340): used initial value expression for variable "arg_copy" because variable was never assigned a value  Warning: Using design file TSE_NIOS_clock_2.vhd, which is not specified as a design file for the current project, but contains definitions for 10 design units and 5 entities in project Info: Found design unit 1: TSE_NIOS_clock_2_edge_to_pulse-europa Info: Found design unit 2: TSE_NIOS_clock_2_slave_FSM-europa Info: Found design unit 3: TSE_NIOS_clock_2_master_FSM-europa Info: Found design unit 4: TSE_NIOS_clock_2_bit_pipe-europa Info: Found design unit 5: TSE_NIOS_clock_2-europa Info: Found entity 1: TSE_NIOS_clock_2_edge_to_pulse Info: Found entity 2: TSE_NIOS_clock_2_slave_FSM Info: Found entity 3: TSE_NIOS_clock_2_master_FSM Info: Found entity 4: TSE_NIOS_clock_2_bit_pipe Info: Found entity 5: TSE_NIOS_clock_2  Regards Cris

[Altera_Forum]

Go to Project -> Add Files and explicitly add your source files. Right now it is implicitly reading in files, which obviously opens you up to possible problems. (That being said, I would estimate half the designs I see implicitly read in files and they're fine with it, so you really don't have to worry about it as long as you understand it.)

[Altera_Forum]

Unfortunately these warnings are normal. 

I file a bug with Altera a while ago about them and got a response they'd be fixed in a new release sometime...  You can patch the code for the first one yourself. The second one you can add the files yourself but if you change anything in sopc you'll be out of sync.  SOPC builder needs to be updated to properly add all the file to the project.