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Honored Contributor I
1,082 Views

Quartus does not recognize bad port declaration

Regarding a given port declaration given like this : 

 

ENTITY john_doe IS 

PORT 

clk : IN STD_LOGIC; 

reset_n : IN STD_LOGIC; 

address : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ; 

read : OUT STD_LOGIC := '0'; 

data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); 

request : IN STD_LOGIC; 

valid : STD_LOGIC 

); 

 

END john_doe ; 

 

Quartus does not recognize the missing "IN" / "OUT" tag above. 

 

How are these signals handeled ? Does Quartus "look" for the component declaration in the top module, where this entity is used?
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Highlighted
Honored Contributor I
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Quartus II assume that the port is by default a IN port. 

 

If you try to assign a value to the signal VALID, Quartus II will then return an error saying "that you try to assign a value to a input port"
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Highlighted
Honored Contributor I
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Why would Quartus II 'assume' anything? 

 

Has anyone filed an SR on this or is this documented anywhere?
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Highlighted
Honored Contributor I
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Quartus follows the VHDL standard, which says that a port declaration without a mode defaults to IN. 

 

Josh
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Highlighted
Honored Contributor I
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Ah!. 

 

I love being able to learn something now every day. 

 

Thanks for the reply, I am now a little smarter (?). 

Let's hope that the decay rate of the remaining brain cells is less then the learning rate for todays new awareness. 

 

Cheers
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Highlighted
Honored Contributor I
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It helps to have a copy of the VHDL standard sitting on your desk. :) Personally, I think VHDL would be better off without this "feature". And everyone says VHDL is a verbose language!  

 

Josh
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Highlighted
Honored Contributor I
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--- Quote Start ---  

Quartus follows the VHDL standard, which says that a port declaration without a mode defaults to IN. 

 

Josh 

--- Quote End ---  

 

 

Bingo!:) (and another Bingo, to meet the requiriement of writing at least 10 charaters to be able to post)
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