Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)

Clock input

Altera_Forum
Honored Contributor II
1,116 Views

Hey, 

 

On my board already wired clock net to regular stxII180 i/o pin 

1. there is any way to change it so that my device will treat it as clock input without the need to do any phisycal changes? 

2. There is a way to connect it to a pll input? 

 

I will appreciate any ideas 

 

Thanks!
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
339 Views

No. The more things you route through, the more jitter can get on the line. The clock pin is special because it routes directly to the PLL. If you come in on another pin, it has to route to the PLL. From a physical perspective, there is no way to get around this. 

Be careful about reading too much into this warning. It's telling you that it could be better, which is nice if you haven't laid out your board. It's not telling you that you will have horrible jitter. What's your requirement? What are you measuring as the output jitter? Are you getting failures? (My guess is your current setup is fine, but I don't know without understanding your requirements.)
0 Kudos
Reply