Quartus fitter quits unexpectedly when using LVDS IO on MAX V

[Disturbed_Pastry]

I'm trying to output an LVDS signal from my MAX V, but every time I try to run the fitter with a LVDS IO standard for the IO bank Quartus throws me a "The Quartus Prime software quit unexpectedly" window, with the following message from the report attached to it:

Internal Error: Sub-system: FYGR, File: /quartus/fitter/fygr/fygr_cdr_op.cpp, Line: 2874

I've tried adding the ALTLVDS IP to my outputs, but that doesn't seem to resolve this issue at all.

What does that message actually mean in terms of whuy the fitter's failing, and how do I fix it?

Thanks

[ShengN_Intel]

Hi,

Could you provide the design file as well?

[ShengN_Intel]

Hi,

Any further update? Possible to provide the design?

Thanks,

Regards,

Sheng