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Honored Contributor I
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Quartus ii stuck at Analysis and Synthesis

Hi all! 

 

My compilation of the VHDL project is stuck at 40% of Analysis and Synthesis status for more than 10 hours. 

It just freeze there, no error. The program is still running since the timing clock at right button corner is still counting. The task manager shows that it still has large RAM usage but with low CPU usage. 

 

Then I use ModelSim to do a fast compile, everything is compiling successfully. 

I am not sure what happened in this case. 

Thanks for help!
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Honored Contributor I
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Compilation in modelsim and quartus are two different things. 

Modelsim just compiles your code for simulation - and will simulate your code exactly as you wrote it. 

Quartus has to convert your code into logic, which is should behave the same way that you write the code. 

 

Long synthesis times usually occur when you have a large ram that does not map to internal ram because your code does not match the behaviour of the ram, so Quartus has to build the ram out of logic. This will use a lot of system ram and CPU time. 

 

If you post your code, maybe we can tell you where you're going wrong.
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Honored Contributor I
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Many thanks for your help. 

 

My project is to design a device with 100 memory block using M20K memories on Stratix V chips. 50 of these memories, let's say m_1 to m_50, have a initialization file. The rest, m_51 to m_100, do not have mif file. The ram code I generated from the Wizard is shown as follows: 

LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; ENTITY mem IS PORT ( clock : IN STD_LOGIC := '0'; data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); rdaddress : IN STD_LOGIC_VECTOR (6 DOWNTO 0); wraddress : IN STD_LOGIC_VECTOR (6 DOWNTO 0); wren : IN STD_LOGIC := '0'; q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ); END mem; ARCHITECTURE SYN OF mem IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0); BEGIN q <= sub_wire0(31 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( address_aclr_b => "NONE", address_reg_b => "CLOCK0", clock_enable_input_a => "BYPASS", clock_enable_input_b => "BYPASS", clock_enable_output_b => "BYPASS", enable_ecc => "FALSE", intended_device_family => "Stratix V", lpm_type => "altsyncram", numwords_a => 128, numwords_b => 128, operation_mode => "DUAL_PORT", outdata_aclr_b => "NONE", outdata_reg_b => "CLOCK0", power_up_uninitialized => "FALSE", ram_block_type => "M20K", read_during_write_mode_mixed_ports => "DONT_CARE", widthad_a => 7, widthad_b => 7, width_a => 32, width_b => 32, width_byteena_a => 1 ) PORT MAP ( address_a => wraddress, address_b => rdaddress, clock0 => clock, data_a => data, wren_a => wren, q_b => sub_wire0 ); END SYN  

 

What i do is to adding new architecture code to it since I think the only different is the mif file, thus what I do is as follows: 

 

LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; ENTITY mem IS PORT ( clock : IN STD_LOGIC := '0'; data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); rdaddress : IN STD_LOGIC_VECTOR (6 DOWNTO 0); wraddress : IN STD_LOGIC_VECTOR (6 DOWNTO 0); wren : IN STD_LOGIC := '0'; q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ); END mem; ---------------------------------------------- -- architecture of m_51 to m_100 -- no mif architecture ---------------------------------------------- ARCHITECTURE SYN OF mem IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0); BEGIN q <= sub_wire0(31 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( address_aclr_b => "NONE", address_reg_b => "CLOCK0", clock_enable_input_a => "BYPASS", clock_enable_input_b => "BYPASS", clock_enable_output_b => "BYPASS", enable_ecc => "FALSE", intended_device_family => "Stratix V", lpm_type => "altsyncram", numwords_a => 128, numwords_b => 128, operation_mode => "DUAL_PORT", outdata_aclr_b => "NONE", outdata_reg_b => "CLOCK0", power_up_uninitialized => "FALSE", ram_block_type => "M20K", read_during_write_mode_mixed_ports => "DONT_CARE", widthad_a => 7, widthad_b => 7, width_a => 32, width_b => 32, width_byteena_a => 1 ) PORT MAP ( address_a => wraddress, address_b => rdaddress, clock0 => clock, data_a => data, wren_a => wren, q_b => sub_wire0 ); END SYN ----------------------------------------- -- architecture for m_1 with mif file -- m1.mif ----------------------------------------- ARCHITECTURE SYN0 OF mem IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0); BEGIN q <= sub_wire0(31 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( address_aclr_b => "NONE", address_reg_b => "CLOCK0", clock_enable_input_a => "BYPASS", clock_enable_input_b => "BYPASS", clock_enable_output_b => "BYPASS", enable_ecc => "FALSE", init_file => "m1.mif", -- memory initialization intended_device_family => "Stratix V", lpm_type => "altsyncram", numwords_a => 128, numwords_b => 128, operation_mode => "DUAL_PORT", outdata_aclr_b => "NONE", outdata_reg_b => "CLOCK0", power_up_uninitialized => "FALSE", ram_block_type => "M20K", read_during_write_mode_mixed_ports => "DONT_CARE", widthad_a => 7, widthad_b => 7, width_a => 32, width_b => 32, width_byteena_a => 1 ) PORT MAP ( address_a => wraddress, address_b => rdaddress, clock0 => clock, data_a => data, wren_a => wren, q_b => sub_wire0 ); END SYN0; ----------------------------------------- -- architecture for m_2 with mif file -- m2.mif ----------------------------------------- ARCHITECTURE SYN1 OF mem IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0); BEGIN q <= sub_wire0(31 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( address_aclr_b => "NONE", address_reg_b => "CLOCK0", clock_enable_input_a => "BYPASS", clock_enable_input_b => "BYPASS", clock_enable_output_b => "BYPASS", enable_ecc => "FALSE", init_file => "m2.mif", -- memory initialization intended_device_family => "Stratix V", lpm_type => "altsyncram", numwords_a => 128, numwords_b => 128, operation_mode => "DUAL_PORT", outdata_aclr_b => "NONE", outdata_reg_b => "CLOCK0", power_up_uninitialized => "FALSE", ram_block_type => "M20K", read_during_write_mode_mixed_ports => "DONT_CARE", widthad_a => 7, widthad_b => 7, width_a => 32, width_b => 32, width_byteena_a => 1 ) PORT MAP ( address_a => wraddress, address_b => rdaddress, clock0 => clock, data_a => data, wren_a => wren, q_b => sub_wire0 ); END SYN1; .......  

 

I am not sure if this is what cause the problem. 

 

Or I have to create 50 individual entity using wizard? 

 

Thanks again for your help!
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Honored Contributor I
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Having multiple architectures will not do anything unless you explicitly select them when you instantiate the ram.  

 

But I doubt this is what's causing the long compile time. Have you got any other code you've written yourself?
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Honored Contributor I
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Thank you for your help. 

 

I do pick different architectures on the upper level for the corresponding memory, where I do the port mapping. 

 

The original version of my project is to input the data to each m_1 to m_50 in the testbench first, then do the sorting operation. It works fine but take long time to simulate. Thus I decide to cancel the inputting data process but add an mif file to each memory. Then I am experiencing this issue. 

 

Here is how I pick the corresponding architecture and the port mapping: 

entity processor is port(......); end entity; architecture proc_rt0 of processor is component control_unit is port( ... ports for this component ... ); end component control_unit; component mem is port( clock : in std_logic := '0'; data : in std_logic_vector (31 downto 0); rdaddress : in std_logic_vector (6 downto 0); wraddress : in std_logic_vector (6 downto 0); wren : in std_logic := '0'; q : out std_logic_vector(31 downto 0) ); end component mem; signal m1_data : std_logic_vector(31 downto 0); signal m1_rdad : std_logic_vector(6 downto 0); signal m1_wrad : std_logic_vector(6 downto 0); signal m1_wren : std_logic := '0'; signal m1_q : std_logic_vector(31 downto 0); for m_1: mem use entity work.mem(SYN0);--------------------------------pick corresponding architecture begin m_1 : mem port map( clock => node_clock, data => m1_data, rdaddress => m1_rdad, wraddress => m1_wrad, wren => m1_wren, q => m1_q ); node_control_unit : control_unit port map ( ...... -- other ports mapping ...... -- port connect to m_1 cu_m1_data => m1_data, cu_m1_rdad => m1_rdad, cu_m1_wrad => m1_wrad, cu_m1_wren => m1_wren, cu_m1_q => m1_q ); end architecture proc_rt0; architecture proc_rt1 of processor is component control_unit is port( ... ports for this component ... ); end component control_unit; component mem is port( clock : in std_logic := '0'; data : in std_logic_vector (31 downto 0); rdaddress : in std_logic_vector (6 downto 0); wraddress : in std_logic_vector (6 downto 0); wren : in std_logic := '0'; q : out std_logic_vector(31 downto 0) ); end component mem; signal m1_data : std_logic_vector(31 downto 0); signal m1_rdad : std_logic_vector(6 downto 0); signal m1_wrad : std_logic_vector(6 downto 0); signal m1_wren : std_logic := '0'; signal m1_q : std_logic_vector(31 downto 0); for m_1: mem use entity work.mem(SYN1);--------------------------------pick corresponding architecture begin m_1 : mem port map( clock => node_clock, data => m1_data, rdaddress => m1_rdad, wraddress => m1_wrad, wren => m1_wren, q => m1_q ); node_control_unit : control_unit port map ( ...... -- other ports mapping ...... -- port connect to m_1 cu_m1_data => m1_data, cu_m1_rdad => m1_rdad, cu_m1_wrad => m1_wrad, cu_m1_wren => m1_wren, cu_m1_q => m1_q ); end architecture proc_rt1;  

 

Then I use the similar way to pick the corresponding architecture for the processor in the upper entity. 

 

After I do some research online, I found the following page on altera website to do the initialization ram with multiple mif file which is the case I need to do. But it use verilog HDL, I am wondering if there is any way I can do it in the same way with vhdl? 

 

https://www.altera.com/support/support-resources/knowledge-base/solutions/rd11172006_639.html (https://www.altera.com/support/support-resources/knowledge-base/solutions/rd11172006_639.html

 

Thanks again for your help!
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