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Quartus ip-generate command: List of available components

Altera_Forum
Honored Contributor II
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Dear all, 

 

At the moment I am trying to port a project from the Arria X to the Arria V GZ. This project contains an PCIe interface and for performing simulations, a virtual root complex is necessary. Within the project, the root complex is generated for the Arria X device via the "ip-generate" command (see below). I tried to convert the command to that of the Arria V GZ in a straight forward manner (see below), but this seems not to be working because the component "altera_pcie_a5_tbed" does not exist. I have been looking for a list of available components of the ip-generate command to see if there is a similar component available for the Arria V GZ, but I cannot find them anywhere. Do you know where I could find such a list? 

 

Cheers, 

Wendo 

--- 

Original Arria X command (in which ip_generate is a reference to $QUARTUS_ROOTDIR/sopc_builder/bin/ip-generate) 

ip_generate --component_name=altera_pcie_a10_tbed --output-directory=./rootport_hwtcl/ --system-info=DEVICE_FAMILY=Arria\ 10 --component-parameter=apps_type_hwtcl=7 --component-parameter=gen123_lane_rate_mode_hwtcl=Gen3\ (8.0\ Gbps) --component-parameter=lane_mask_hwtcl=x8 --component-parameter=pld_clk_MHz=250 --component-parameter=port_type_hwtcl=Native\ endpoint --component-parameter=serial_sim_hwtcl=1 --component-parameter=millisecond_cycle_count_hwtcl=124250 --component-parameter=pll_refclk_freq_hwtcl=100\ MHz --component-parameter=deemphasis_enable_hwtcl=false --component-parameter=ecrc_check_capable_hwtcl=0 --component-parameter=ecrc_gen_capable_hwtcl=0 --component-parameter=enable_pipe32_phyip_ser_driver_hwtcl=0 --component-parameter=use_crc_forwarding_hwtcl=1 --report_file=spd:./rootport_hwtcl.spd --file-set=SIM_VERILOG --verbose # "${SIM_ROOT}/altera_pcie_a10_tbed/altera_pcie_a10_tbed_hw.tcl" --search-path=${SIM_ROOT}/altera_pcie_a10_tbed/,\$ --component-parameter=millisecond_cycle_count_hwtcl=248500 

 

Altered command for Arria V GZ: 

 

ip_generate --component_name=altera_pcie_a5_tbed --output-directory=./rootport_hwtcl/ --system-info=DEVICE_FAMILY=Arria\ 5\ GZ --component-parameter=apps_type_hwtcl=7 --component-parameter=gen123_lane_rate_mode_hwtcl=Gen3\ (8.0\ Gbps) --component-parameter=lane_mask_hwtcl=x8 --component-parameter=pld_clk_MHz=250 --component-parameter=port_type_hwtcl=Native\ endpoint --component-parameter=serial_sim_hwtcl=1 --component-parameter=millisecond_cycle_count_hwtcl=124250 --component-parameter=pll_refclk_freq_hwtcl=100\ MHz --component-parameter=deemphasis_enable_hwtcl=false --component-parameter=ecrc_check_capable_hwtcl=0 --component-parameter=ecrc_gen_capable_hwtcl=0 --component-parameter=enable_pipe32_phyip_ser_driver_hwtcl=0 --component-parameter=use_crc_forwarding_hwtcl=1 --report_file=spd:./rootport_hwtcl.spd --file-set=SIM_VERILOG --verbose --search-path=${SIM_ROOT}/altera_pcie_a5_tbed/,\$ --component-parameter=millisecond_cycle_count_hwtcl=248500
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