Quartus issuing error message for Memory Interface design

[Altera_Forum]

Hi, 

 I have two interfaces PCI and DDR2 memory controllers targeting same FPGA of Cylcone III family. When I ran that case I am getting the following errors. Can some one explain what it exactly says.  Error: Clock input port inclk[0] of PLL "ddr2_example_top:mem_top|ddr2:ddr2_inst|ddr2_controller_phy:ddr2_controller_phy_inst|ddr2_phy:ddr2_phy_inst|ddr2_phy_alt_mem_phy:ddr2_phy_alt_mem_phy_inst|ddr2_phy_alt_mem_phy_clk_reset:clk|ddr2_phy_alt_mem_phy_pll:pll|altpll:altpll_component|altpll_jeg3:auto_generated|pll1" must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control block  Info: Input port INCLK[0] of node "ddr2_example_top:mem_top|ddr2:ddr2_inst|ddr2_controller_phy:ddr2_controller_phy_inst|ddr2_phy:ddr2_phy_inst|ddr2_phy_alt_mem_phy:ddr2_phy_alt_mem_phy_inst|ddr2_phy_alt_mem_phy_clk_reset:clk|ddr2_phy_alt_mem_phy_pll:pll|altpll:altpll_component|altpll_jeg3:auto_generated|pll1" is not connected

[Altera_Forum]

Check where the input clock of your PLL is coming from. The clock source you use is not allowed and therefore disconnected. 

 Regards, Ton

[Altera_Forum]

But I didn't select any PLLs here, Will memory interface mega core uses PLL. Can you provide me some more details. And the Quartusn is pointing to some sub design regarding the input that I have specified

[Altera_Forum]

There´s certainly a PLL inside the DDR2 controller. So the clk input of the controller leads to the PLL. I can´t check on a short notice it for you, because the controller doesn´t show up in my IP list. Probably there´s something misconfigured over here. Maybe someone else can help you for this.You are using SOPC builder I suppose? 

 Good luck, Ton

[Altera_Forum]

I generated it from ALtera Mega wizard, I observed in the docs provided that DDR2 controller utilizes one PLL. Ok thanks for replying let me wait for others to reply.