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Altera_Forum
Honored Contributor I
1,788 Views

Quartus message re output drivers

Quartus gives me a message about no output drivers on pins. I have tried putting the .alt driver on the pins, no difference. So what drivers am I supposed to put on the pins?? 

The quantity of useless messages output by the compiler is daunting. And half of them seem to be un-necessary. So why do it?
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8 Replies
Altera_Forum
Honored Contributor I
216 Views

Can you post an example of one such message - including whether it's a 'warning', 'error' or 'info' message? 

 

The vast quantity of 'useless messages' are there to help you determine whether Quartus has interpreted your design correctly. If Quartus is stating there is not driver on an output signal, when you think there should be (for instance), then the messages allow you to pick up on that. 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
216 Views

Warning (10034): Output port "A0" at mainMCB65_8.v(134) has no driver 

 

Its a yellow triangle one, not sure what that is. 

The program presumably thinks I should have a driver there. 

I have been trying to do the Quartus tutorial, but it wont run properly. Does the intro and then stops. I have been looking for info on the Quartus website, but that doesn't seem to work too well either. 

Re the messages, I understand the idea, but a great many of the messages are superfluous or repeated. For instance, the program tells me three times that I have no clocks specified. Correct. I am using the system clock while I debug. Does it really need to give me this message three times?
Altera_Forum
Honored Contributor I
216 Views

Then I get this warning: 

Warning (169064): Following 32 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results 

These pins are a memory bus, and although you can draw a bidirectional pin on the .BDF drawing, it comes with no output enable. How are you supposed to do that?
Altera_Forum
Honored Contributor I
216 Views

Then when I try to create the vhd file I get loads of this warning series. 

Warning (275016): Found Altera-specific megafunction, primitive or component "7400" 

Error (275069): Design file contains illegal characters for Verilog HDL 

Error (275069): Design file contains illegal characters for Verilog HDL 

Error (275069): Design file contains illegal characters for Verilog HDL 

The 7400 I am using is an Altera function. Why on earth would it have illegal characters in it? 

There is no information given on how to resolve this, or where to find the problem.
Altera_Forum
Honored Contributor I
216 Views

 

--- Quote Start ---  

Then when I try to create the vhd file I get loads of this warning series. 

Warning (275016): Found Altera-specific megafunction, primitive or component "7400" 

Error (275069): Design file contains illegal characters for Verilog HDL 

Error (275069): Design file contains illegal characters for Verilog HDL 

Error (275069): Design file contains illegal characters for Verilog HDL 

The 7400 I am using is an Altera function. Why on earth would it have illegal characters in it? 

There is no information given on how to resolve this, or where to find the problem. 

--- Quote End ---  

 

 

7400 parts are very old. 

7400 is not a legal name to give anything in VHD or Verilog, as it contains only numbers. VHDL and Verilog identifiers must start witha character.  

I suggest you use parts other than the 7400 ones if you want to convert to HDL
Altera_Forum
Honored Contributor I
216 Views

The 7400 comes from a Quartus library, and is put into the .BDF file. Why would Quartus supply a library file that would not work in their program? 

That makes no sense. 

I have since spent more time, and recompiled the program, and the messages go away. I deleted the .V file and forced the program to use the .BDF file. 

It appears that when both files are present, Quartus will corrupt the .V file.
Altera_Forum
Honored Contributor I
216 Views

 

--- Quote Start ---  

The 7400 comes from a Quartus library, and is put into the .BDF file. Why would Quartus supply a library file that would not work in their program? 

That makes no sense. 

I have since spent more time, and recompiled the program, and the messages go away. I deleted the .V file and forced the program to use the .BDF file. 

It appears that when both files are present, Quartus will corrupt the .V file. 

--- Quote End ---  

 

 

It works perfectly fine - it just will not convert to legal Verilog (because it is a very old library, back from when HDL was used far less used.) 

The problem you had was that the .v file with illegal syntax took preference over the .bdf file
Altera_Forum
Honored Contributor I
216 Views

Yes, I re-arranged the project files, removed the .V file and put in the.BDF. It compiles fine with few warnings. Now if I could get the non-working pins to work! Are any of the pins on JP1 and JP2 used for other functions? Is there some place where you have to change their function to straight I/O? 

And how can you use the 32M ram chip in a hardware design?
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