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Quartus produces different synthesis for same design.


I synthesized my design in Quartus for Arria 10 in a remote server. In my memory instantiation, it is saying that it is unable to infer a Block RAM due to asynchronous reads. I tried to synthesize again in my local machine, this time setting a DE1-SoC FPGA as the target device. It properly inferred my memory instantiations as BRAMs. To test my sanity, I decided to bring it to board level in my DE1; the design functioned as expected. I'm just wondering why Quartus produces different synthesis for the same design? Are there some compiler commands that I can use to force Quartus to infer my memory instantiations as BRAM? This is significant since I am unable to produce accurate timings and area estimates. Thank you.


From the terminal in remote Server:

Quartus Prime Design Software

Version 17.1.1 Build 273 12/19/2017 Patches 1.38 SJ Pro Edition


Please let me know if you need information from the log files.


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Could you help to share your design so I can check on this?