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SHard2
Novice
218 Views

Warning: field in quartus report that was not expected

Hi

I am using Quartus 19.1.0 (patch 0.02std) and DSP Builder with Matlab R2013a.

Executing 'Verify Design' in simulink with the 'Run Quartus Prime Software' option ticked gives the following error in the Matlab window.

 

<snip>

MyModel: Simulation Passed

[fit_success, fit_details] = dspba.runHWCompilation(MyModel, './')

Running ...

Executing 'C:\intelFPGA\19.1\quartus\bin64\quartus_sta.exe -t ../rtl/MyModel/MyModel_Source.tcl overwrite >quartus.out 2>&1' in './'

Warning: field in quartus report that was not expected: Required

 with value: 280.033604032

 

> In C:\intelFPGA\19.1\quartus\dspba\Blocksets\BaseBlocks\extract_details_struct_from_csv_data.p>extract_details_struct_from_csv_data at 19

 In C:\intelFPGA\19.1\quartus\dspba\Blocksets\BaseBlocks\run_quartus.p>run_quartus at 110

 In C:\intelFPGA\19.1\quartus\dspba\Blocksets\BaseBlocks\+dspba\runHWCompilation.p>runHWCompilation at 95

 In C:\intelFPGA\19.1\quartus\dspba\Blocksets\BaseBlocks\+dspba\verifyModel.p>verifyModel at 276

 In C:\intelFPGA\19.1\quartus\dspba\Blocksets\BaseBlocks\+dspba\MatlabCommandCallback.p>MatlabCommandCallback at 27 

Quartus Prime Compilation successful

--------------------------------------

 <snip>

 

The verification then quits and does not provide any timing result.

 

Any advice on how best to deal with this would be greatly appreciated.

 

many thanks

Simon

 

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12 Replies
CheePin_C_Intel
Employee
80 Views

Hi Simon,

 

As I understand it, you seems to observe some issue when trying to call Quartus compilation from DSP Builder with your design.

 

Would you mind to the following to help narrowing the issue and finding potential workaround:

 

  1. Would you mind to try compile the generated Quartus project, in standalone Quartus.
  2. It is recommended for your to try using the latest Q19.4Pro + DSP Builder to see if issue still existing? Just to isolate version dependent issue.

 

Please let me know if there is any concern. Thank you.

 

 

Best regards,

Chee Pin

CheePin_C_Intel
Employee
80 Views

Hi,

 

I understand that you have posted a note and uploaded a QAR which could replicate the issue. Sorry if there is any confusion. I am unable to locate the file. Would you mind to re-post here? And also share with me the detail step to replicate the issue. I might not have the right tool to perform issue replication due to lock down. However, I will try my best to debug. Sorry for the inconvenience.

 

By the way, just wonder if you have had a chance to try with the workarounds in my previous notes?

 

Thank you.

CheePin_C_Intel
Employee
80 Views

Hi,

 

Sorry for confusion. I notice that your note appear in the All Updates but not in All Communities section and I am not still unable to locate the file that you are attaching. Would you mind to try log on to the Forum and attach the file to see if can get through? Thank you very much.

CheePin_C_Intel
Employee
80 Views

Hi,

 

Just wonder if you have had a chance to try with the previous workaround to see if it works to isolate out the Matlab:

 

  1. Would you mind to try compile the generated Quartus project, in standalone Quartus.

 

Thank you very much.

 

SHard2
Novice
80 Views

Good morning again,

I have replied immediatly to all of your emails. I do not understand why none are making it through your system to you?

I have also replied both by email and via the forum.

This is an urgent problem for us, and we urgently need advice.

I will send this once again through both the portal and by replying to the email.

Your questions regarding your proposed work arounds are included below from my original reply.

Regards

Simon

 

 

**** Previous emails are below ****

Good morning,

I did reply to your first email, did you not receive it? I have included it at the end of my reply.

I have attached a zip file, I hope it makes it through your firewall?

Best regards

Simon

 

 

<snip>

Good morning and thank you for getting back to me.

(Q 1) Would you mind to try compile the generated Quartus project, in standalone Quartus.

 

 

The design will compile correctly and pass timing if I select the following from within the Simulink menu.

DSP Builder -> Run Quartus Prime Software

However if I select the following from within the Simulink menu to open the ‘DSP – Verification’ window.

DSP Builder -> Verify Design

The verification fails with the errors in my first email.

 

(Q 2) It is recommended for your to try using the latest Q19.4Pro + DSP Builder to see if issue still existing? Just to isolate version dependent issue.

 

 

Unfortunately I cannot upgrade Quartus as I am targeting a Stratix IV device which restricts me to Quartus Standard Edition V19.1, this device family is not supported by Quartus Pro.

The install is on Windows 10 64-bit and I have also installed the required patch.

I am using the DSP Builder Advanced Blockset and, according to the intel document ‘hb_dspb_intro.pdf’, I cannot upgrade MATLAB.

The latest compatible version for Quartus Standard Edition V19.1 is MATLAB R2013a.

I cannot find this error listed on the Intel/Altera website as a problem that has been raised previously.

 

 

(On a separate PC I have an old setup of MATLAB R2012a and Quartus V13.0.1 installed on windows 7 64 bit. This error does not occur on this older version.)

If you can offer any advice it would be greatly appreciated.

Best regards

 

</snip>

SHard2
Novice
80 Views

posted a file.
SHard2
Novice
80 Views

 

Hi again

I have just noticed that the link in your email opens a different support case than the one I have showing under ‘My Intel->MySupport’

The original case is request number 04558711 and has some of my replies to you listed.

 

The link you sent to me opens a different case with none of my replies visible?

Your link does not seem to have a case request number that I can see??

 

***** Additional previous replies *****

Hi

Looking a bit deeper there seems to be an extra field inserted in the auto generated 'demo_nco_NCOSubsystem.tcl' file.

Line 91 sets the field names as...

"Logic,ALM_Logic_Regs,ALM_Logic,ALM_Regs,ALM_Mem,Comb_Aluts,Comb_ALUT_Logic,Comb_ALUT_Route,Mem_ALUT,Regs,Regs_1,Regs_2,ALM,DSP,FP_DSP,Mem_Bits,MLAB_Bits,M20K,IO,FMax,Slack,Required"

The field values themselves are added one-by-one, but an extra field entry is added on line 138...

"print_csv $fmax"

This field has no name and therefore causes the error reported in the Matlab command window.

I am unable to simply comment this line out as the file is regenerated each time the verification test is run.

If you can offer any advice it would be gratefully received.

We are seeing exactly the same error in our actual development models, so it is not limited to the examples.

Best Regards

Simon

CheePin_C_Intel
Employee
80 Views

Hi,

 

Thanks for your update. I can see your update now. I believe you are posting them directly into the portal. I can see the demo_ncl.zip as well.

 

As I understand it from your notes, I understand that the design is passing Quartus compilation. Issue only occurs when you click on Verify Design. Also, I understand that there is no issue when you are running with different (older) versions of MATLAB and Quartus. Based on these observation, the issue seems to be related to interaction between the specific version of DSP Builder and Quartus but not the design or Quartus issue.

 

To avoid further gating your progress, you may try the following two workarounds tested working by you:

 

1. Running compilation with Quartus and then perform analysis on the compilation result without using Verify Design.

 

2. Try with the other setup of yours with MATLAB R2012a and Quartus V13.0.1 which is working.

 

At the same time, I will try to perform issue replication on my side. For your information, currently, I do not have the specific setup ie Q19.1Std and MATLAB R2013a installed in my PC. I will try with other version available in my PC to see if can replicate the observation. Once replicated, I will file a case to Factory for future fix.

 

Please let me know if there is any concern. Thank you.

 

Best regards,

Chee Pin

 

CheePin_C_Intel
Employee
80 Views

Hi,

 

For your information, I notice that the demo_nco is an example in the DSP Builder. I have tested running with MATLAB R2015a + Q17.0Std using the built in demo_nco. Note that these are the software version that I have in my local PC. There is no issue when I run the DSP Builder -> Verify Design -> Run Verification. The design can pass Simulation, Quartus and Timing tests. Based on the observation to-date, I believe the issue is specific to Q19.1Std or compatibility between Q19.1Std and MATLAB R2013a. I would recommend you to proceed with either of the two workarounds mentioned in my previous post to avoid gating your progress. Sorry for the inconvenience.

 

Please let me know if there is any concern. Thank you.

 

Best regards,

Chee Pin

 

SHard2
Novice
80 Views

​Hi Thanks you for getting back to me.

I thought this would be the case as it works OK on my older installation.

 

Will you be submitting this as a bug to the development team?

 

Also, I noticed you are using MATLAB R2015a, is this OK to use?

According to the documentation  I can only use R3013a with the latest Quartus Std edition.

 

Best Regards

Simon

 

 

 

 

 

 

 

 

 

CheePin_C_Intel
Employee
80 Views

Hi Simon,

 

thanks for your help and understanding. When I am back to office after lock down, I will work on testing with the specific MATLAB and Quartus version to replicate the issue. Once it is replicated, then I can file a case to Engineering.

 

Regarding the R2015a, yes, you are right. The formal supported version is R2013a with Qstd. Since I only have R2015a and Q17.0Std installed, so, I use them to try out for testing purpose only. Sorry for any confusion.

SHard2
Novice
80 Views

​Good morning

Thank you for clarifying this for me

and thanks again for your assistance with this.

 

Best regards

Simon

 

 

 

 

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