I have a problem in which I am trying to design a butterfly PUF (butterfly latch circuit) using d-types.
When I try to synthesise this circuit quartus will show that it is using 0 logic cells from my FPGA yet when I click to view the RTL netlist it will show everything correctly. I have tried using dff primitives, as well as lcells but nothing seems to work.
Surely having 2 dff primitives on the FPGA would contribute to 2 logic cells being used right? Isn't that partially the point of primitives?
Is there a way to force quartus to synthesize my verilog module EXACTLY as I have written it so that it does not perform any sort of optimization/minimization on it?
Does your design actually drive anything? If it's a purely internal piece of logic then, yeah, Quartus will optimize it out with standard settings.
The simplest way to stop it optimizing it out is to add a noprune constraint to the output signal. Note that if it's optimizing it out in a "real" design rather than a test one, it has a reason for removing it that you'll need to investigate.
Hope that helps,
You can also go to the Verilog file -> right click -> insert template -> find the attribute for the 1 you want. This will list down all the available attribute where Quartus offers.