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JBeau2
Beginner
969 Views

Impossible to generate a preloader with cyclone V

Hello,

I have a problem to generate the preloader with the DE0_Nano_Soc.

The configuration is the following:

Quartus Lite 18.01 and DS5 standard edition V18.01 on Windows 10,

I created a sample project following the documentation: SoC-FPGA Design Guide DE0-Nano-SoC Edition / LAP – IC – EPFL / Version 1.32 of Sahand Kashani-Akhavan & René Beuchat.

I can compile the quartus project without error but with a lot of warning: (826).

Then I ran BSP-Editor without problem.

Then I change the directory and launch the command “make”:

cd C:\intelFPGA\18.1\DE0_Nano_Soc_demo\hw\quartus\software\spl_bsp

make

I had to modify the path environment variable as follow:

QUARTUS_ROOTDIR                    C:\intelFPGA\18.1\quartus

SOPC_KIT_NIOS2                         C:\intelFPGA\18.1\nios2eds

QSYS_ROOTDIR                            C:\intelFPGA\18.1\quartus\sopc_builder\bin

 

But I got this error:

Error No rule to make target DS5 uboot-socfpga.tar.gz needed by uboot-socfpga/.untar

What can I do ?

Thanks for your help

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1 Reply
AnandRaj_S_Intel
Employee
55 Views

Hi,

 

This issue comes when using SOC EDS tool to generate the preloader. After creating the new HPS and BSP settings file, make command is giving a failure

Check below link:

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base...

 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

 

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)

 

 

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