Quartus reporting unconstrained inputs and outputs on constrained paths

[TMayd]

Hi I have implemented a set of timing constraints on my Arria 10 design and I'm confused about two things. [Running Quartus Pro 22.1]

1. Quartus is reporting one of my input clocks (it is a differential clock, I'm not sure if this matters) as an unconstrained input port.

I have set the clock constraint as:
create_clock -name {chs_clk_rx} -period 150.000MHz [get_ports {chs_clk_rx}];

*I know the -period 150.000MHz is odd but the timing analyzer accepts it. I have additional input clock pins that are also differential signals that I set, for example:

create_clock -name {lvds_rx_1} -period 150.000MHz [get_ports {s1_lvds_in[1]}];

This signal does not show up as an unconstrained input port. Is there any reason why one might show up differently than the other? 

2. I have a whole bunch of differential output signals where I have assigned an output delay constraint (or assigned a generated clock to output clocks) and the negative pin of the differential pair is showing up as unconstrained.

My understanding with differential pair timing constraints is we only constrain the positive edge so that the timing analyzer doesn't try to run two separate paths. Is this incorrect?

An example of the constraint in question:
create_generated_clock -name lvds_tx_1 -source [get_pins {i_pll_lvds|iopll_0|altera_iopll_i|twentynm_pll|iopll_inst|outclk[1]}] -master_clock [get_clocks {i_pll_lvds|iopll_0|outclk1}] -divide_by 1 -multiply_by 1 [get_ports {s1_lvds_out[1]}]

The positive pin is showing as constrained but the s1_lvds_out[1](n) is showing unconstrained. 

Some advice would be greatly appreciated!

[Nurina]

Hello,

It sounds like you are missing I/O constraints.

On Timing Analyzer, Report Unconstrained Paths and go to Setup/Hold Analysis>Unconstrained Input Ports.

This report should explain what's missing. Also, for the LVDS signal, I think the IP has generated SDC constraints so it doesn't appear as unconstrained input port. You can check Report SDC to see what constraints have been added.

You may find this training useful: https://www.youtube.com/watch?v=GItefNliYpM

Regarding the second question, I will have to investigate further and will update you on this soon.

Regards,

Nurina

[Nurina]

Hello,

You are referring to differential pin pair as shown in this page right?

https://www.intel.com/content/www/us/en/docs/programmable/683143/21-3/assigning-differential-pins.html

Regards,

Nurina

[Nurina]

Hello,

I have consulted LVDS expert.

Below is outcome from our discussion:

The negative pin is only contra from positive pin, the timing is also exactly the same, only inverted in terms of voltage. Timing wise, this is the same timing.

So, if you are using LVDS differential pins for LVDS, then you only need to constraint the positive pin.

If you are using normal IO pin to perform LVDS, then you need to constraint both pins.

I hope this clears things up, please let me know if you have any further questions.

Regards,

Nurina

[Nurina]

Hello,

Do you have any updates?

Regards,

Nurina

[TMayd]

Hi Nurina,

Thanks for getting back to me! I was off for a few days. 

To clarify a bit I am not using the Intel LVDS IP core to drive the signals, but rather our own logic. However in the pin planner I have set the signals to LVDS I/O standard as shown:

The commands I use are:

set_location_assignment PIN_L6 -to chs_clk_rx(n) ; # BANK 3D : 1.8V lpc_la28_n
set_location_assignment PIN_K6 -to chs_clk_rx ; # BANK 3D : 1.8V lpc_la28_p

set_instance_assignment -name IO_STANDARD LVDS -to "chs_clk_rx(n)"
set_instance_assignment -name IO_STANDARD LVDS -to "chs_clk_rx"

set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to "chs_clk_rx(n)" -entity achilles_top
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to "chs_clk_rx" -entity achilles_top

Which are identical to other LVDS pins I'm using.

My output signals are similar:

set_location_assignment PIN_A6 -to s1_lvds_out[0](n) ; # BANK 3E : 1.8V hpc_ha05_n
set_location_assignment PIN_B6 -to s1_lvds_out[0] ; # BANK 3E : 1.8V hpc_ha05_p

set_instance_assignment -name IO_STANDARD LVDS -to "s1_lvds_out[0](n)"
set_instance_assignment -name IO_STANDARD LVDS -to "s1_lvds_out[0]"

Is there a constraint I'm missing by not using the Intel LVDS IP core? 

Thanks,

Tyler

[Nurina]

Hello,

In this case you are using the dedicated LVDS block inside the FPGA, so you only need to assign constraint on the positive pin. In this case I would also suggest you to do the same for the assignments you have added in your .qsf/.tcl file; only set them for the positive pin, it would automatically be applied on the negative pin.

If you are using normal IO to form LVDS, only then you need to assign constraints for both pins.

Regards,

Nurina

[TMayd]

Hi Nurina thanks for your response.

So I removed those constraints from the pin.tcl file and deleted them in .qsf so that it would be properly re-assigned. 

When I run: report_ucp -panel_name "Unconstrained Paths"

I still see:
chs_clk_rx:  No input delay, min/max delays, false-path exceptions, or max skew assignments found

I have definitely constrained this signal as a clock because when I run: "report_clocks" it is clearly listed:
chs_clk_rx Base 6.666 150.0 MHz 0.000 3.333

The tcl setting for this pin is:
set_location_assignment PIN_K6 -to chs_clk_rx ; # BANK 3D : 1.8V lpc_la28_p
set_instance_assignment -name IO_STANDARD LVDS -to "chs_clk_rx"
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to "chs_clk_rx" -entity achilles_top

I'm not sure why I'm seeing this issue. I have other clocks constrained identically, for example:

set_location_assignment PIN_B5 -to s1_lvds_in[0] ; # BANK 3E : 1.8V hpc_ha09_p
set_instance_assignment -name IO_STANDARD LVDS -to "s1_lvds_out[0]"
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to "s1_lvds_in[0]" -entity achilles_top

The only difference is that "chs_clk_rx" is coming into a global clock pin and going into a PLL whereas the other signals are not. 

I'm also still seeing on the report unconstrained signals that my (n) output pins are all still showing up as unconstrained. 

Is there a restriction to using the IO_STANDARD LVDS when you are NOT using the Intel LVDS IP CORE to drive the signals? 

Thanks,

Tyler

[TMayd]

Sorry to be clear I did run a full recompile after making those changes. 

[Nurina]

Hello Tyler,

When I run: report_ucp -panel_name "Unconstrained Paths"

I still see:

chs_clk_rx: No input delay, min/max delays, false-path exceptions, or max skew assignments found

I have definitely constrained this signal as a clock because when I run: "report_clocks" it is clearly listed:

chs_clk_rx Base 6.666 150.0 MHz 0.000 3.333

This report is saying that you have not set any I/O timing constraints. Yes you have created the clock but since this clock is at the I/O pin, Timing Analyzer expects I/O constraints such as set_input_delay, set_min_delay, set_max_delay, etc.

You may find this video training useful: https://www.youtube.com/watch?v=ggWxledaBFg&t=1085

I'm not sure why I'm seeing this issue. I have other clocks constrained identically, for example:

set_location_assignment PIN_B5 -to s1_lvds_in[0] ; # BANK 3E : 1.8V hpc_ha09_p

set_instance_assignment -name IO_STANDARD LVDS -to "s1_lvds_out[0]"

set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to "s1_lvds_in[0]" -entity achilles_top

Have you added I/O constraint to this path? If not, can you share your .qar file so I can investigate further? To generate this, go to Project>Archive Project.

I'm also still seeing on the report unconstrained signals that my (n) output pins are all still showing up as unconstrained. 

Is there a restriction to using the IO_STANDARD LVDS when you are NOT using the Intel LVDS IP CORE to drive the signals? 

You can ignore the unconstrained paths reported at (n) pins, so that Timing Analyzer won't run two separate path. As long as you are using the LVDS block in the FPGA, you can use IO_STANDARD LVDS.

Regards,

Nurina

[Nurina]

Tyler,

Can you share your device OPN?

Thanks,

Nurina

[TMayd]

Hi Nurina,

The device I'm using is the 10AS066H2F34I1SG

I'm confused what you mean by the "LVDS BLOCK". What is that? Is that simply what pins are used when assigning to the IO_STANDARD LVDS? 

I watched the video you linked and I am still confused. As I put I have reported the clocks and the offending clock clearly shows up as a defined clock in the "report clocks":
chs_clk_rx Base 6.666 150.0 MHz 0.000 3.333

But it is still showing as unconstrained. Are you saying that even clocks require input delays? That doesn't really make sense, since you have to refer the those delays to some kind of clock? 

I am not sure I can provide a .QAR file through the forum due to proprietary concerns. I have set the following constraints in my SDC:
create_clock -name {chs_clk_rx} -period 150.000MHz [get_ports {chs_clk_rx}];
create_clock -name {lvds_rx_1} -period 150.000MHz [get_ports {s1_lvds_in[1]}]; 

The first signal does not show as constrained but the second does. They're both clocks but only the CHS_CLK_RX goes into a PLL. Could that cause any difference?

[Farabi]

case re-assign to LVDS support engineer.

regards,

Farabi

[Nurina]

Hello Tyler,

This case falls under LVDS area, so it has been reassigned to LVDS expert.

[AqidAyman_Intel]

Hi Tyler,

I think it is better to share the .qar design for this project in order for us to further investigate this and if it is potentially a bug, we need it to report to the engineering team. You no need to share the full design, it is sufficient to share the one that related to this issue only for us to reproduce the issue from our end. You can share the file through email for privacy. I will initiate the email first.

Regards,

Aqid

[TMayd]

Hi Aqid,

Thank you. I have responded to your email.

Tyler