Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Quartus v13.0, QSys possible bug in passing parameters

Altera_Forum
Honored Contributor II
‎05-12-2013 04:14 AM
1,051 Views

QSys from Quartus v13.0 on my PC does not pass any component parameters to the generated master Verilog file. Like if you instantiate a video sync generator component, you will not see any of its parameters passed to the Verilog source file. Could anyone confirm?

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