QuartusII bug - What to do with it?

[Altera_Forum]

Hi, first of all i would like to refer you to the problem in the altera.com site: 

in Altera_site : solution id: rd02162011_810 (Sorry, the site doesnt allow me to write here links)   I try to implement an altlvds with external pll in dpa mode. The data rate is 750MHz and the parallel clock is 125MHz. When trying to do so, the above critical warning is issued.   Just for the record, I have tried the suggested fix and it didnt fix it.   I just want to know whether I can write the exported version of the fpga or this bug really causes the pll configuration to be invalid.   And if I cant do so, what should I do, considering the fact that the same bug occuring in all of the quartus versions (including 11)?   Thank you, Itay.

[Altera_Forum]

hi, Can somebody please reply to this? 

Its really important to me and i'm stuck on it. Thanks in advance...

[Altera_Forum]

The said support solution refers to ALTLVDS_TX megafunction. DPA mode however is only available for ALTLVDS_RX. So apparently, it doesn't apply to your problem. There may be a similar bug, but it needs to be analyzed in detail.

[Altera_Forum]

First of all thank you for answering. 

And about my problem, what should I do now? just test to see if it works?

[Altera_Forum]

I would check the gate level netlist if there are errors similar to the problem describe in the support solution: registers clocked with wrong frequency. Reviewing the warning exactly would be the first step. It should refer to origin of the problem.