Questa always return X state on output

[HalmonCelman]

Hi,

I'm on CentOS 7 and I've installed Quartus Prime Lite 21.1

I'm trying to run simple simulation in Questa.

my *.bdf file:

 my *.vwf file

 when i'm running Simulation>Run Functional Simuation

Simulation normally starts and new window appears, only problem is that in this window output still have an  X state:

 

am I doing something wrong or it is a bug?

if it's the bug is there any way to fix it?

I would be grateful for any response.

HalmonCelman

[RichardTanSY_Intel]

Hi,

I am able to simulate the design successfully at my side.

My guess is most likely the NOT gate is not connected to the input and output port.

Could you move the NOT gate around to see if the line still connected? You may check the RTL viewer to confirm.

Best Regards,

Richard Tan

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 9/10 survey.

[HalmonCelman]

Hi,

Thank you for your response,

I tried to move gate and wires are still connected, also I have run RTL viewer, result:

HalmonCelman

[RichardTanSY_Intel · Accepted solution]

I think it might be the Questa tool issue. I was using Modelsim previously.

Could you try to use Modelsim Intel FPGA edition instead of Questa and see if the issue persists?

Best Regards,

Richard Tan

[HalmonCelman]

I've installed Modelsim Intel FPGA edition and I set it in settings to use, but nothing changes - still same window

[RichardTanSY_Intel]

That's weird. I able to see the result with Modelsim but not with Questa.

Could we setup a Team call meeting so you could share screen and show me how it goes?

Nativelink simulation flow seems to be working for Questa. Perhaps you can try that as well.

Best Regards,

Richard Tan

[HalmonCelman]

 Of course

I would be grateful for such a meeting ( maybe I'm doing something wrong, then this meeting would clear it up ), when could it be ?

About Nativelink simulation, I'm still newbie at this things so I don't know how to properly write scripts to run simulation, so I would prefer at start to don't have to do that.

HalmonCelman

[RichardTanSY_Intel]

You may refer to the User Guide below to set up the Nativelink environment.

https://www.intel.com/content/www/us/en/docs/programmable/683102/21-3/setting-up-nativelink-simulation.html

Picking up from where you are left, you may generate the testbench in the simulation waveform editor or write your own testbench.

Then set up the testbench in the User Guide step4, Assignment > Setting > Simulation. Turn on Compile test bench. Click Test Benches to add testbench. Specify the testbench name and the top level module in testbench.

Once set up complete, go to Tools> Run simulation tools > Run RTL simulation.

Questa Intel FPGA Edition software should pop up and simulate the result.

Best Regards,

Richard Tan

[RichardTanSY_Intel]

Thanks for acknowledge the solution provided. 

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thank you.

Best Regards,

Richard Tan

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 9/10 survey.