I have a Quartus vhdl project consisting of about 10 vhdl libraries and about 150 vhdl files.
Would like to create an IP from it in order to instantiate to a bigger design.
The same project for xilinx FPGAs is being easily encapsulated into IP by "Create and package IP" command in Vivado .
Could not find an similar functionality with Qsys/Platform Designer (e.g. to read the project qpf file instead of manually specifying all the files). And could not find a way to group files in libraries while adding them to Qsys project.
The library pragma is not supported since it is Quartus Pro
Is there any practical way to do it?
This seems like a duplicate of this thread: https://community.intel.com/t5/Programmable-Devices/How-to-create-IP-from-a-multy-library-vhdl-project-in-Quartus/m-p/1424902#M87474
I will close this case and respond to your questions on the above thread.
p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution, give Kudos and rate 4/5 survey