Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Question About Graphic editor

Altera_Forum
Honored Contributor II
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I am new with the graphic editor. How do I label the nets for error signals instead of directly connect them? Thanks.

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Altera_Forum
Honored Contributor II
1,005 Views

is it erroring out in Analysis and Synthesis? can you post the error. 

 

i'm not sure if the required AHDL syntax can do [0:3], try [3:0]. other than that it looks like it should work
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Altera_Forum
Honored Contributor II
1,005 Views

I tried using [0..3]. It works now. So we can not use [0:3] format, right?

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Altera_Forum
Honored Contributor II
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seems that way, you could try searching for AHDL documentation if this is legal or not. glad its working :)

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Altera_Forum
Honored Contributor II
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Another question is that I have a input signal goes to 5 places. Do I need to use a buffer when I edit the gdf? Does the software will automatically assign a buffer for it after synthesize? Thanks.

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Altera_Forum
Honored Contributor II
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no, you can just have an input pin and connect it to all of the destinations using a point to point net or using the named nets like you have in your example

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Altera_Forum
Honored Contributor II
1,005 Views

Thanks for your answer.

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Altera_Forum
Honored Contributor II
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I am migrating an old design(Quick Work) using Max Plus II. Do you know how to realize the attached schematic use Max Plus II. Thanks for your help.

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