Question about Example 1-22 of Quartus Prime TimeQuest Timing Analyzer Cookbook

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Question about Example 1-22 of Quartus Prime TimeQuest Timing Analyzer Cookbook

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In Example 1-22 of "Quartus Prime TimeQuest Timing Analyzer Cookbook", the latency of clk_a and clk_b is specified. clk_a and clk_b are in the different clock_groups. However, if is normal that they are not used in set_input_delay and set_output_delay. Why should the latency and clock_groups for clk_a and clk_b be specified if they are used in the set_input_delay and set_out_delay?

Also

set input_max [expr $Td_max + $Tco_max]

set input_min [expr $Td_min + $Tco_min]

# Create the input delay constraints when clk_a is selected

set_input_delay

-clock virtual_source_clk_a

-max $input_max

[get_ports datain]

set_input_delay

-clock virtual_source_clk_a

-min $input_min

[get_ports datain]

Are there the differences in the clock paths missing in $input_max and $input_min?

Thanks

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