Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15322 Discussions

Question about Example 1-22 of Quartus Prime TimeQuest Timing Analyzer Cookbook

Altera_Forum
Honored Contributor II
788 Views

In Example 1-22 of "Quartus Prime TimeQuest Timing Analyzer Cookbook", the latency of clk_a and clk_b is specified. clk_a and clk_b are in the different clock_groups. However, if is normal that they are not used in set_input_delay and set_output_delay. Why should the latency and clock_groups for clk_a and clk_b be specified if they are used in the set_input_delay and set_out_delay?  

 

Also  

set input_max [expr $Td_max + $Tco_max] 

 

set input_min [expr $Td_min + $Tco_min] 

 

# Create the input delay constraints when clk_a is selected 

 

set_input_delay  

-clock virtual_source_clk_a  

 

-max $input_max  

 

[get_ports datain] 

 

set_input_delay  

 

-clock virtual_source_clk_a  

 

-min $input_min  

 

[get_ports datain] 

 

 

Are there the differences in the clock paths missing in $input_max and $input_min?  

 

Thanks
0 Kudos
0 Replies
Reply