[Question about synchronous transfer] Will this kind of transfer cause problem?

[Altera_Forum]

I know for any asynchronous data transfers, we would need special handling mechanisms (i.e double sync, FIFO, handshaking, etc). I have a design that where the core logic interacts with the LVDS TX IP block using 2 PLLs. The launch clock (that feed the core reg) is from the 1st PLL. The latch clock (that feeds the tx_reg from LVDS) is from 2nd PLL, but is also sourced from the first PLL. These 2 clocks have the same frequency but different phase. In this case, is this kind of transfer still considered synchronous or will it run into metastability issue despite meeting timing requirement in TQ? 

 I attached a diagram for better illustration. The transfers that I posted is from core reg --> tx_reg   ​Thank you.

[Altera_Forum]

This is still a synchronous system. 

 Why are you using two PLLs though? A single PLL with two output clocks, and a relative phase-shift between them would be more appropriate.  You can also dynamically phase-shift the PLL clocks. Using this you can sweep over the output data and determine what the optimal setup/hold time is for your system (and the amount of timing margin).  I posted controller code in this thread:  http://www.alteraforum.com/forum/showthread.php?t=46527  Cheers, Dave