Question on Schematic to VHDL conversion.

[Altera_Forum]

I'm new to programable logic, most of my experience has been with microcontrollers. I know a little about VHDL but not enough right now to program with it. I do know schematics and so I designed my project using schematic files. I would like to learn VHDL and I thought it could be helpful to look at the VHDL that Quartus II generated from my schematic design. First thing I noticed is the VHDL is smaller that I expected. I have multiple pages that interconnect. Do I need to create a VHDL file for each page or does Quartus use the sub pages in generating the output code? I was able to follow some of the code as it talks about DFF_inst2 <='1' and I can find inst2 in my schematic. But it also has a bunch of  

 SIGNAL SYNTESIZED_WIRE_22; etc.   I understand what is going on but I would like to know which line in my schematic is SYNTHESIZED_WIRE_22. Some are obvious and I can follow those but when something has nothing but synthesized inputs and outputs I have no clue where those lines are. Is there an easy way to find out and more important can I pre-name all of the lines before I convert it to VHDL? Any help would be greatly appreciated.   Thanks  Steve

[Altera_Forum]

I think, most of your questions can be easily answered by trial. Did you notice the option, to name the signals ("wires") in your schematic? You have to use a correct bitwidth for bus signals, however. When you convert the schematic to VHDL afterwards, you'll see, that this is what your asking for. Synthesized_wire_xx signal names are used for unnamed signals only. 

   --- Quote Start ---  Do I need to create a VHDL file for each page?  --- Quote End ---   Each schematic is representing a design entity. You can replace no, some or all schematic entities by VHDL design entities in your design, as you like. The design's integrity should be kept anyway.

[Altera_Forum]

UNderstanding schematics and moving to HDLs is a good step. Some of the more common HDL mistakes I see are from people that have no concept of the underlying hardware and just write behavioral code. You'll be moving from the other direction, and though at times might write stuff too structural, it tends to be stuff that you understand and that works. 

That being said, I would not rely on the schematic to HDL conversions too much. It's possible to have a wire that has no name on it, and so the conversion has to make something up, where in an HDL everything that exists has a name, so that isn't a problem. If anything, get an HDL book or look at examples on the web. It will be a much better training.  I also believe you're going with the "I know what this schematic does, so what does it look like in HDL". Machine-generated HDL is usually pretty ugly and not the goal to achieve. If you have a simulation/testbench, probably the best thing to do is to try writing the HDL from scratch that mimics the schematic. If you can do that, you'll be learning at a good pace. (And don't forget to use the RTL Viewer a lot, which will give you a visual representation, i.e. schematic, of the HDL you're writing...)

[Altera_Forum]

I wouldnt rely on or use the Schematic -> HDL converter if I could avoid it. Its not that great, and Ive come across bugs with it, mainly with 2D arrays in schematics being converted to 2d std_logic_vectors (that dont exist as a type). The only time Ive used this feature is when I need to run a simulation on a schematic in modelsim. Then you have the problem of the crappy signal naming for unnamed connections (as you've found). 

 I would say learn digital design from the schematic, and then try and write your own version of the schematics file. I dont think the auto-generated VHDL is going to teach you alot.