Quick Question - How to event on multiple clocks rising edges?

[Altera_Forum]

Very quick question... 

 If I have two clocks of different speeds, and want something to happen when the rising edge of both clocks occur at the same time.... how do I do this?   I have tried a few different ways, but am relatively new to VHDL...e.g. I tried something like:    if ((intRCLK'EVENT) and (intRCLK = '1')) then if((MULT_CLK'EVENT) and (MULT_CLK='1')) then Load_State <= Load_Byte1; else Load_State <= Load_IDLE; end if; end if;    But got errors such as:   error (10820): netlist error at lvds_fifo_control.vhd(229): can't infer register for load_state[0] because its behavior depends on the edges of multiple distinct clocks   and:   error (10822): hdl error at lvds_fifo_control.vhd(221): couldn't implement registers for assignments on this clock edge   I know I am going about this in the wrong way, but I don't really know what approach to take with this.  As always, any pointers or help greatly appreciated!

[Altera_Forum]

Hi. 

I think what you want to do is quite impossible with conventional digital logic.  I can give a very general idea. If you know that one clock is faster than the other you can detect the moment in which one edge overcomes the other. With a (dangerous) use of inverter delay you can then try to detect the delay between the edges.  However, I repeat, this is very difficult.  Hope some other reader can provide a better solution.

[Altera_Forum]

Hmm, The two different speed clocks are essentially the same clock, but fed through a PLL... 

 The second clock is exactly 4x the speed of the first. I was intending to use when the faster clock and slower clock rise at the same time, to show me where the start of a cycle is. This is because I have a statemachine with 4 stages which I need to complete within one slow clock cycle, so thought if I had a 4x clock then when they clock together it triggers the first stage, then the statemachine can run from the faster clock. Using when both clocks rise together to keep the state machine synchronised to the main clock.   Is there a better technique to do this then, rather than what I have been attempting?

[Altera_Forum]

There is no such thing as a register that is clocked off two edges. I'm not sure what you're trying to do, as no edges occur at the same time(as the resolution gets smaller, at some point they will be different). You can either do something combinatorially with the clocks(like AND them), or have registers based off each one independently and do the logic after that.

[Altera_Forum]

--- Quote Start ---  Hmm, The two different speed clocks are essentially the same clock, but fed through a PLL...The second clock is exactly 4x the speed of the first. I was intending to use when the faster clock and slower clock rise at the same time, to show me where the start of a cycle is.   --- Quote End ---    This is possible as long as the edges of both clocks are aligned, which depends on the PLL configuration. Use a clock enable for this purpose. But better don't use the slower clock directly as clock enable. Toggle one data signal with the slower clock, and read this signal with the faster one.  However, I would recommend against this until you are more familiar with synchronous designs.

[Altera_Forum]

Hi Rysc, 

 I have just been reading one of your older posts (http://www.alteraforum.com/forum/archive/index.php/t-1024.html), and realised that I have not been thinking how this maps to the hardware and actual registers...   I then thought if i use the event and level of the slower clock and just the level of the faster clock then I should be able to sort it out...   e.g.  Loader_start_state : process (intRCLK, MULT_CLK) begin if (rst = '1') then Ld_firstbyte <= '0'; else if ((intRCLK'EVENT) and (intRCLK = '1') and (MULT_CLK='1')) then Ld_firstbyte <= '1'; else Ld_firstbyte <= '0'; end if; end if; end process Loader_start_state;    But I still get the error:   error (10822): hdl error at lvds_fifo_control.vhd(219): couldn't implement registers for assignments on this clock edge  I have seen this error before when trying to write on rising and falling edges of the same clock, but now I am just using the faster clocks level, so surely this assignment is only made on the rising edge of the intRCLK?   Sorry I am still pretty new to VHDL and struggling a little...

[Altera_Forum]

The problem is, your code doesnt really follow a template quartus can recognise as a real bit of hardware. What you're asking it to do is put '1' on the "Ld_firstbyte" signal only when the clock rises, and then drop back to '0' when the clock is stable again. This is not a register or any real logic. Some fixes: 

 1. You need rst in the sensitivity list, else reigsters wont reset in simulation unless there is a clock. 2. Remove MULT_CLK from the sensitivity list. 3. Put the MULT clk inside the intRCLK clk tree. What you want is this:   Loader_start_state : process (rst, intRCLK) begin if (rst = '1') then Ld_firstbyte <= '0'; elsif ((intRCLK'EVENT) and (intRCLK = '1') then --why not use the rising_edge function isntead? if(MULT_CLK='1')) then Ld_firstbyte <= '1'; else Ld_firstbyte <= '0'; end if; end if; end process Loader_start_state;   As an asside - using clocks directly for logic is usually a BAD THING.

[Altera_Forum]

PS- why not just run everything at the fast clock speed and use clock enables when you want stuff to happen. it makes life (and designs) SOOOO much simpler than having multiple clock domains. Synchronisation isnt a problem for a start.

[Altera_Forum]

Cheers for the advice... I'll give it a go!

[Altera_Forum]

You shouldn't AND the clocks, because that will give glitches. 

You could use the falling edge of the fast clock to detect the start of the slow clock. And either use the falling fast clock to clock your state machine, or start the state machine running on the rising clock with this pulse you just generated. In the latter case you have doubled the speed requirement, so there will be an upper limit on the fast clock.

[Altera_Forum]

I think I am overdesigning what I am trying to do... as I am pretty sure there will be an easier way to do this. 

 I am clocking into my FPGA some 24-bit parallel data using the first clock that I described.   I was then trying to use a faster clock to control a state machine to multiplex the 24bit data into an 8 bit FIFO.    I originally tried doing this with a clock that was 3x the speed of the original clock, but found that due to the write producing a one cycle delay, my third byte that was written contained the data from the next word appearing at the 24bit parallel input.    To combat this I wanted to use a clock 4x the speed of the original clock to allow the three bytes to be clocked in, and then a dummy byte not being clocked into the FIFO, so that the entire word could be clocked in by the fast clock in one clock cycle of the slower original clock without loosing anything due to the write delay.   However I need the multiplexing to be synchronised with the slow bus aswell as the fast bus so that I capture the entire 24 bit word rather than the second and third byte of a one word, and the first byte of the next.   Thanks for everyones suggestions so far, but being new to VHDL and I feel I may be getting a little lost in it all... please be patient with me, and know that any and all help is greatly appreciated!    What is the easiest way to multiplex these incoming 24bit words into an 8bit FIFO (The 24bit input comes from a 24bit parallel LVDS interface if that helps at all??)

[Altera_Forum]

I haven't read all the replies so I may be saying something redundant. Can you attack the problem from a different approach. Suppose all we are really looking for is a moment when the two clocks are both high. Use the faster clock to sample the slower clock. Provide registers for metastability and edge detection. Use the edge detect as the enable for your logic which is driven from the faster clock. 

 Jake

[Altera_Forum]

It's alright I was over complicating things loads, and it appears to be simulating correctly now... 

 I already had one state machine running from the slow clock, and then the load state machine on the faster clock to load in all 3 bytes from each word.   I just used a signal generated in the first statemachine (that is synchronised to the slow clock) called Load_FIFO to cause the load state machine to move from the IDLE state into loading the firstbyte into the FIFO. I just have to make sure the clock was 4 times the speed not 3, and include a dummy state in the load state machine to compensate for the 1 clock delay in writing each byte....   Seems to be working so far.. but thanks everyone for all their comments...

[Altera_Forum]

I agree with the josyb solution. 

 Run a state machine on the falling edge of the fast clock. The state machine counts for consecutive low levels of the slow clock, then it enables a second state machine clocked on the rising edge of the fast clock that will be enabled when both slow and fast clock are rising (or something like that).   P.S. How many answers. Your question has triggered the FPGA design people :-)

[Altera_Forum]

--- Quote Start ---  I agree with the josyb solution. Run a state machine on the falling edge of the fast clock.  --- Quote End ---    What ???? Why on earth complicate things with both falling and rasing edges. There is absolutely no need for that.  I agree with Tricky. By far, the simplest solution is to run the whole thing on a single clock (single edge, of course), and use a clock enable.  If for some reason it is still desirable to use the slow clock as well, then it is pretty simple to have a clock enable on the fast clock that is synced to the slow clock. Both clocks are edge aligned because they are just different multiples on the same PLL.     --- Quote Start ---  P.S. How many answers. Your question has triggered the FPGA design people :-)  --- Quote End ---    Indeed :)

[Altera_Forum]

As there is a Fifo in play, the solution can be as simple as: 

Use a DCFIFO of 24 bits wide and write the data into this fifo with the slow Clk1x. Then at the read side use a clock of at least 3 times the frequency to read 24 bits out of the fifo and multiplex the 24 bits into packets of 8 bits.  Don't try to dodge clock domain crossing (as Tricky advises), it will come back and haunt you (no pun intended with the upcoming Halloween frenzy).

[Altera_Forum]

It seems to me, that the discussion is partly ignoring the fact, that both clocks are said to be sourced from one PLL. They aren't unrelated, you don't need domain crossing techniques for it and Quartus is generally able to deal with the timing relation of both clocks. It does this correctly in various situations, e.g. with software SERDES.

[Altera_Forum]

I overlooked the fact that both clocks come from the same PLL. In that case one can set "CLOCKS_ARE_SYNCHRONIZED" to "TRUE" saving a bit on logic resources and decreasing latencies. The 'rdempty' signal going (or staying) inactive tells when to start (or continue) the state machine to 'unpack' the 24 bits into 8 bit packets.