R-tile intel FPGA IP for compute express link(CXL) testbench has an AVY_ERROR.

[senwang]

Hi, hope you have a nice day!

I have a problem when using the R-tile intel FPGA IP for compute express link(CXL) testbench. The testbench is generated through Quartus Prime 24.3. The CXL ip version is 1.14. And I refer to the  "Agilex™ 7 R-Tile Compute Express Link* (CXL*) FPGA IP Design Example User Guide" for simulation. 

But when I  run_cmd_t1_vcs_DTL.sh script, it will end up with an error message of

"AVY_ERROR:log@479218.844ns:[ACXL2_8_1_1n1] Receive an unknown CXL DVSEC ID 'h50 in CXL Entity (BDF fnuc_aa_0_0) "

I don't know why. My environment variables have been set correctly, and I also have the relevant licenses. Is this a version issue or something.

[RongYuan]

Hi,

Please confirm that you have absolute paths for all licenses setup as shown in "4.1.1. VCS Tools and License".

Also confirm PIPE Mode Simulation is enabled before generating an example design.

Regards,

Rong

[senwang]

Hi RongYuan，

Thank you for your suggestions!

Below is the confirmation and analysis based on your requests:

 VCS Tools and related licenses (AVERY_PCIE/AVERY_PLI) have all been configured with absolute paths in environment variables（the user guide mentions）。

In the 24.3 version of Quartus that I am using, the PIPE mode is enabled by default and does not involve this issue.

I would like to know if it is possible to determine where the problem may have occurred through this AVY_ERROR analysis.

Thanks

[RongYuan]

Hi,

I'm not able to replicate your issue. My suggestion is to double check the design example user guide and follow exact the same versions of software and design.

Regards,

Rong

[RongYuan]

Hi,

Please use the same versions of software tools described in UG.

Regards,

Rong