RAM write and read

Altera_Forum · ‎07-05-2016

Hello,

I little bit confused with dual port RAM,my target is write and read data.I want to write data.like on the certain positions will be 128 and on the rest positions will be just 0.

I reading this article https://www.altera.co.jp/ja_jp/pdfs/...s_qii51007.pdf (https://www.altera.co.jp/ja_jp/pdfs/literature/hb/qts/qts_qii51007.pdf)

and I think I need true dual port Ram.

 library ieee;                                                
    use ieee.std_logic_1164.all;                    
    entity true_dual_port_ram_single_clock is     
generic (                    
      DATA_WIDTH : natural := 8;                    
      ADDR_WIDTH : natural := 6     );                    
     port (      clk : in std_logic;            
addr_a : in natural range 0 to 2**ADDR_WIDTH - 1;      
addr_b : in natural range 0 to 2**ADDR_WIDTH - 1;      
data_a : in std_logic_vector((DATA_WIDTH-1) downto 0);      
data_b : in std_logic_vector((DATA_WIDTH-1) downto 0);      
we_a : in std_logic := '1';
      we_b : in std_logic := '1';      
q_a : out std_logic_vector((DATA_WIDTH -1) downto 0);     
q_b : out std_logic_vector((DATA_WIDTH -1) downto 0)                
     );    
end true_dual_port_ram_single_clock;                
    architecture rtl of true_dual_port_ram_single_clock is     
-- Build a 2-D array type for the RAM     
subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);     
type memory_t is array((2**ADDR_WIDTH - 1) downto 0) of word_t;     -- Declare the RAM signal        
     shared variable ram : memory_t;                                                
begin     process(clk)     begin     if(rising_edge(clk)) then -- Port A                    
      if(we_a = '1') then     
         case addr_a is
        when 0 =>
        data_a <= 128;
        when 16 =>
        data_a <= 128;
        when others =>
        data_a <=0;
        end case;
       ram(addr_a) <= data_a;                    
       -- Read-during-write on the same port returns NEW data                    
       q_a <= data_a;      else                    
       -- Read-during-write on the mixed port returns OLD data                    
       q_a <= ram(addr_a);      end if;                    
     end if;     end process;                    
     process(clk)    
 begin     
if(rising_edge(clk)) then -- Port B                    
      if(we_b = '1') then      
 ram(addr_b) := data_b;     
  -- Read-during-write on the same port returns NEW data      
 q_b <= data_b;                    
      else       
-- Read-during-write on the mixed port returns OLD data       
q_b <= ram(addr_b);            
      end if;  
   end if;     
end process;           
     end rtl;

Could you pls give any guidance for my code?

Altera_Forum · ‎07-06-2016

any ideas?

Altera_Forum · ‎07-06-2016

why even bother with a ram if all you are doing is translating the address? why not just a LUT or even just input decoder?

Altera_Forum · ‎07-11-2016

could you pls give an example in this case?With LUT or decoder?

Altera_Forum · ‎07-11-2016

--- Quote Start ---

why even bother with a ram if all you are doing is translating the address? why not just a LUT or even just input decoder?

--- Quote End ---

could you pls give an example in this case?With LUT or decoder?